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首页> 外文会议>Conference on Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications Ⅳ, Jul 30, 2002, Boston, USA >Optimising Parallel Programs for Hardware Implementation
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Optimising Parallel Programs for Hardware Implementation

机译：优化并行程序以实现硬件

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摘要

This paper describes an approach for optimizing hardware designs produced from software languages extended with constructs for parallel execution and hardware processing, such as the Handel-C language. Our aim is to optimize these programs by applying transformations that include the appropriate amount of parallelism, in order to obtain the best trade-offs in space and in time. These transformations can be applied automatically at compile time, enabling the programmer to adapt parallel programs rapidly to a specific hardware platform. Our transformational approach, which involves design sequentialisation and parallelisation, contains two novel features. First, we develop an algorithm for sequentialising parallel programs. This algorithm relaxes the scheduling of the original design, giving a scheduler the freedom to arrange it to achieve better results in speed, in size, or in both. Second, we combine this sequentialisation algorithm with pipeline vectorization, a technique known to reduce the execution delay of loops by pipelining the loop body. We adapt several transformation techniques used in vectorizing and parallelizing software compilers, such as loop unrolling and loop tiling, to widen the applicability of our method. Results show that our approach often works well: for instance a manually pipelined convolution design, for implementation in a Xilinx XC4000 device produced from a Handel-C description, is speeded up by over 2 times by our prototype compiler.
机译：本文描述了一种优化硬件设计的方法，该软件是从软件语言产生的，该软件语言扩展了并行执行和硬件处理的结构，例如Handel-C语言。我们的目标是通过应用包括适当数量的并行性的转换来优化这些程序，以便在空间和时间上获得最佳的权衡。这些转换可以在编译时自动应用，从而使程序员能够将并行程序快速适应特定的硬件平台。我们涉及设计序列化和并行化的转换方法包含两个新颖的功能。首先，我们开发一种用于顺序化并行程序的算法。该算法放宽了原始设计的计划，使计划程序可以自由地安排它，从而在速度，大小或两者上取得更好的结果。其次，我们将这种序列化算法与流水线矢量化相结合，该技术通过流水线化循环主体来减少循环的执行延迟。我们采用了矢量化和并行化软件编译器的几种转换技术，例如循环展开和循环平铺，以扩大我们方法的适用性。结果表明，我们的方法通常行之有效：例如，通过原型编译器将手动流水线卷积设计（在由Handel-C描述制作的Xilinx XC4000器件中实施）实现了两倍以上的速度。

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