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首页> 外文会议>Consumer Electronics, Communications and Networks (CECNet), 2012 2nd International Conference on >Floating-point error and its effect analysis of digital pre-distortion
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Floating-point error and its effect analysis of digital pre-distortion

机译：数字预失真的浮点误差及其影响分析

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The power amplifier of the radio repeater often works in the nonlinear regime to improve its efficiency, which will not only cause a lower SNR and mutual interference between the channels, but also increase the error rate of the signals transmitted in their own channels. This paper utilizes the pre-distortion technology to solve the problem and applies the QRD_RLS self-adaptive algorithm to realize the DPD in FPGA. The data truncation errors in FPGA are operated and stored by a finite floating point. Based on results of DPD, the rise of baseline is analyzed in this paper. This paper proves that error is the leading cause to the rise of baseline. Moreover, the errors caused by the truncate operation are discussed, and the method of reducing truncation errors is also demonstrated. After optimization, the SNR of the circuit grows more than 35 dB, the ACPR improves 20 dB and the influence of errors is limited to merely 3dB.
机译：无线电转发器的功率放大器通常在非线性状态下工作以提高其效率，这不仅会导致较低的SNR和通道之间的相互干扰，还会增加在其自己通道中传输的信号的错误率。本文利用预失真技术解决了这一问题，并采用QRD_RLS自适应算法在FPGA中实现了DPD。 FPGA中的数据截断错误由有限的浮点运算和存储。基于DPD的结果，分析了基线的上升。本文证明了误差是导致基线上升的主要原因。此外，讨论了由截断操作引起的错误，并介绍了减少截断错误的方法。经过优化后，电路的SNR增长超过35 dB，ACPR提高20 dB，误差的影响仅限于3dB。

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