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首页> 外文会议>Design, Automation Test in Europe Conference Exhibition;DATE 2013 >Stochastic degradation modeling and simulation for analog integrated circuits in nanometer CMOS
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Stochastic degradation modeling and simulation for analog integrated circuits in nanometer CMOS

机译：纳米CMOS中模拟集成电路的随机退化建模与仿真

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摘要

Reliability is one of the major concerns in designing integrated circuits in nanometer CMOS technologies. Problems related to transistor degradation mechanisms like NBTI/PBTI or soft gate breakdown cause time-dependent circuit performance degradation. Variability and mismatch between transistors only makes this more severe, while at the same time transistor aging can increase the variability and mismatch in the circuit over time. Finally, in advanced nanometer CMOS, the aging phenomena themselves become discrete, with both the time and the impact of degradation being fully stochastic. This paper explores these problems by means of a circuit example, indicating the time-dependent stochastic nature of offset in a comparator and its impact in flash A/D converters.
机译：可靠性是在纳米CMOS技术中设计集成电路的主要问题之一。与诸如NBTI / PBTI之类的晶体管降级机制或软栅极击穿相关的问题会导致与时间有关的电路性能下降。晶体管之间的可变性和失配只会使这种情况更加严重，而同时晶体管老化会随着时间的流逝而增加电路中的可变性和失配。最后，在先进的纳米CMOS中，老化现象本身变得离散，时间和退化影响完全是随机的。本文通过电路示例探讨了这些问题，指出了比较器中失调随时间的随机性及其对闪存A / D转换器的影响。

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