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Design intention application to tolerance-based manufacturing system

机译：设计意图在基于公差的制造系统中的应用

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Continuous shrinkage of design rule (DR) in ultra-large-scale integrated circuit (ULSI) devices brings about greater difficulty in the manufacturing process. The keys to meeting small process margin are adequate extraction of critical dimension (CD) tolerance for each object and budgeting the tolerance for each process step. Furthermore, to extract adequate tolerance, design intent in terms of electrical behavior should be carefully considered. Electrical behavior is carefully verified in both cell and chip design phases with respect to timing, IR drop, signal integrity, crosstalk, etc., using various electronic design automation (EDA) tools. However, once the design data is converted to layout data and signed off, most of the design intention is abandoned and unrecognized in the process phase. Thus, instead of essential tolerance according to layout-related design intention, uniform and redundant tolerance is used, and therefore excess tolerance is assigned for some layouts.rnTo solve the problem described above, a tolerance-based manufacturing system utilizing flexible layout-dependent speculation derived from design intention has been discussed . In this paper, a test flow is developed and application to 45nm node test chip is examined.
机译：超大规模集成电路（ULSI）器件中设计规则（DR）的不断缩小给制造过程带来了更大的困难。满足较小工艺裕度的关键是为每个对象充分提取关键尺寸（CD）公差，并为每个工艺步骤预算公差。此外，为了获得足够的公差，应仔细考虑电气性能方面的设计意图。使用各种电子设计自动化（EDA）工具，在单元和芯片设计阶段就时序，IR下降，信号完整性，串扰等方面仔细验证了电气性能。但是，一旦将设计数据转换为布局数据并签名，大部分设计意图就会在过程阶段被放弃并且无法识别。因此，不是根据与布局相关的设计意图的基本公差，而是使用统一的冗余公差，因此为某些布局分配了多余的公差。为了解决上述问题，采用了基于公差的灵活的基于布局的推测的基于公差的制造系统从设计意图得出的讨论。本文开发了一种测试流程，并研究了其在45nm节点测试芯片中的应用。

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