A 10-ns Low-Power 4K Static RAM with Cross-Coupled Thyristor Cells, Made in a Standard Oxide-Isolated Bipolar Process

机译：具有交叉耦合晶闸管单元的10 ns低功耗4K静态RAM，采用标准的氧化物隔离双极工艺制造

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Using a standard oxide-isolated bipolar process with 3 ÃÂ¿m minimum design rules a very fast 4096ÃÂ1 bit static RAM has been realized. This RAM is both ECL-10k and ECL-100k compatible. The power dissipation is low due to the use of low-stand-by-power-consuming cross-coupled thyristor cells and due to high performance circuitry including bit line switching.

机译：使用具有3μm最小设计规则的标准氧化物隔离双极工艺，已经实现了非常快的4096×1位静态RAM。此RAM兼容ECL-10k和ECL-100k。由于使用了低待机功耗交叉耦合晶闸管单元，并且由于包括位线开关在内的高性能电路，因此功耗很低。

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《Eighth European Solid-State Circuits Conference (ESSCIRC '82)》|1982年|P.188-191|共4页
会议地点 Brussels(BE);Brussels(BE)
作者
Grenier D.; Lohstroh J.; Dumont D.; Linssen A.; Crommenacker J.v.d.; Welten F.; Slob A.;
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RTC, Caen, France;

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原文格式 PDF
正文语种 eng
中图分类半导体集成电路（固体电路）;
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1. High-speed, low-power, bipolar standard cell design methodology for Gbit/s signal processing [J] . Koike K., Kawai K. IEEE Journal of Solid-State Circuits . 1998,第10期

机译：用于Gbit / s信号处理的高速，低功耗，双极标准单元设计方法
2. High-speed, low-power, bipolar standard cell design methodology forGbit/s signal processing [J] . Koike K., Kawai K., Onozawa A., IEEE Journal of Solid-State Circuits . 1998,第10期

机译：用于Gbit / s信号处理的高速，低功耗，双极标准单元设计方法
3. Comparative Analysis of Static Characteristics of Insulated Gate Bipolar Transistors and Thyristors with Static Induction [J] . O. I. Bonomorskii, A. S. Kyuregyan, A. V. Gorbatyuk, Russian electrical engineering . 2015,第2期

机译：绝缘栅双极晶体管和晶闸管静态感应的静态特性比较分析
4. A 2 micron high performance bipolar 64K ECL static RAM technology with 200 square microns contactless memory cell [C] . Vora M., Chien F., Burton G., Electron Devices Meeting, 1984 International . -1

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5. A static random access memory cell based on a thin capacitively coupled thyristor device. [D] . Nemati, Farid. 2001

机译：基于薄电容耦合晶闸管器件的静态随机存取存储单元。
6. Canadian Colloquium on Computer-Assisted Interpretation of Electrocardiograms. V. Suggested standards for instrumentation in computer processing of electrocardiograms. [O] . J. D. Sherwood 1973

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7. Design and Implementation of 4 Bit Static RAM through Low-Power Pulse-Triggered Flip-Flop [O] . G. Suresh, N. V. Lalitha, R. Aamani 2015

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A 10-ns Low-Power 4K Static RAM with Cross-Coupled Thyristor Cells, Made in a Standard Oxide-Isolated Bipolar Process

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