This paper describes a parallel architecture for a variety of algorithms for video compression.It has been designed to meet the requirements of encoding and decoding according to the ITU-T standard H.263.The architecture is an implementation of the instruction systolic array (ISA) model which combines the simplicity of systolic arrays with the flexibility of a programmable parallel computer.Although the parallel accelerator unit is implemented on no more than 9mm~2 of silicon it suffices to meet the compression rate necessary to send a compressed video stream through a standard ISDN terminal interface.
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