The Design for Testability of A Virtual Logic Analyzer

机译：虚拟逻辑分析仪的可测试性设计

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Based on the architecture of a virtual logic analyzer with 400MHz/102 Channels, the theory and the method of a kind of design for testability of the virtual logic analyzer is discussed in this paper. The C~(++) program flow charts of the self-test of the virtual logic analyzer through the design for testability are given, which achieve the self-test of its FIFO, its data channels and its system level functions such as trigger word(s) identification, trigger and trace modes and so on.

机译：基于400MHz / 102通道虚拟逻辑分析仪的体系结构，讨论了一种虚拟逻辑分析仪可测试性设计的理论和方法。通过可测试性设计，给出了虚拟逻辑分析仪自测试的C〜（++）程序流程图，实现了其FIFO，数据通道和系统级功能（如触发字）的自测试。（s）识别，触发和跟踪模式等。

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来源
《Fifth International Conference on Electronic Measurement amp; Instruments (ICEMI'2001) Vol.1 Nov 18-21, 2001 Guilin, China》|2001年|p.277-279|共3页
会议地点 Guilin(CN);Guilin(CN)
作者
Yibing Shi; Houjun Wang; Guangju Chen;
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作者单位

Dept. of Automation, University of Electronic Science and Technology of China, Chengdu 610054, P.R.C.;

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会议组织
原文格式 PDF
正文语种 eng
中图分类机械、仪表工业;
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The Design for Testability of A Virtual Logic Analyzer

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