Overlay errors in optical lithography

机译：光刻技术中的重叠误差

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The overlay errors in IC manufacturing must be less than one-third of the minimum linewidth for higher density devices. It is a very important and difficult problem to keep high overlay accuracy. In this paper, a simulation model was made to analyze the overlay distribution geometry and the statistical characteristics. It explores the effects of various parameters of intrafield sources and interfield sources on the overlay. The emphasis is placed on analysis of the physical significance of various parameters.

机译：对于高密度器件，IC制造中的覆盖误差必须小于最小线宽的三分之一。保持高覆盖精度是一个非常重要和困难的问题。在本文中，建立了一个仿真模型来分析覆盖分布的几何形状和统计特征。它探讨了场内源和场间源的各种参数对叠加的影响。重点放在分析各种参数的物理意义上。

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《First international symposium on instrumentation science and technology(ISIST'99)》|1999年|p.497-502|共6页
会议地点 Luoyang(CN);Luoyang(CN)
作者
Zone-Ching Lin; Wen-Jang Wu;
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正文语种 eng
中图分类机械、仪表工业;
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专利

1. An empirical study-based state space model for multilayer overlay errors in the step-scan lithography process [J] . He Fuyun, Zhang Zhisheng RSC Advances . 2015,第126期

机译：基于经验研究的状态空间模型，用于步进扫描光刻过程中的多层覆盖误差
2. Predicting distortions and overlay errors due to wafer deformation during chucking on lithography scanners [J] . Kevin T. Turner Sathish Veeraraghavan and Jaydeep K. Sinha Journal of Micro/Nanolithography,MEMS and MOEMS . 2009,第4期

机译：预测在光刻扫描仪吸盘期间由于晶片变形而引起的变形和覆盖误差
3. The Magnitude of Potential Exposure-Tool-Induced Critical Dimension and Overlay Errors in Double Dipole Lithography for the 65-nm and 45-nm Technology Nodes [J] . Tsann-Bim CHIOU, Alek C. CHEN, Shih-En TSENG, Japanese Journal of Applied Physics. Part 1, Regular Papers & Short Notes . 2004,第6B期

机译：在65纳米和45纳米技术节点的双偶极光刻技术中，潜在的曝光工具引起的临界尺寸和重叠误差的大小
4. Overlay errors in optical lithography [C] . Zone-Ching Lin, Wen-Jang Wu International symposium on instrumentation science and technology . 1999

机译：光学光刻中的覆盖错误
5. Predicting overlay errors on device wafers due to the interaction of optical and EUV lithography fabrication processes [D] . Zheng, Liang 2006

机译：预测由于光学和EUV光刻制造工艺的相互作用而导致的器件晶圆上的覆盖错误
6. Fabrication of three-dimensional suspended interlayered and hierarchical nanostructures by accuracy-improved electron beam lithography overlay [O] . Gwanho Yoon, Inki Kim, Sunae So, -1

机译：通过提高精度的电子束光刻覆盖层来制造三维悬浮层间和分层纳米结构
7. Characterization of waferstepper and process-related front- to backwafer overlay errors in bulk micromachining using electrical overlay test structures [O] . Henk W. van Zeijl, Frans G. C. Bijnen, John Slabbekoorn 2004

机译：使用电覆盖测试结构的散装微机器中的Waferstepper和过程相关的前进覆盖误差的表征

Overlay errors in optical lithography

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