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首页> 外文会议>Formal Methods in Computer-Aided Design, 2009. FMCAD 2009 >Scaling VLSI design debugging with interpolation
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Scaling VLSI design debugging with interpolation

机译：通过插值扩展VLSI设计调试

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摘要

Given an erroneous design, functional verification returns an error trace exhibiting a mismatch between the specification and the implementation of a design. Automated design debugging uses these error traces to identify potentially erroneous modules causing the error. With the increasing size and complexity of modern VLSI designs, error traces have become longer and harder to analyze. At the same time, design debugging has become one of the most resource-intensive steps in the chip design cycle. This work proposes a scalable SAT-based design debugging algorithm that uses interpolants to over-approximate sets of constraints that model the erroneous behavior. The algorithm partitions the original problem into a sequence of smaller subproblems by using subsections of the error trace that are examined iteratively. This is made possible by using interpolants to properly constrain the erroneous behavior for each subproblem, significantly reducing the number of simultaneous time-frames examined in the error trace. The described method is shown to be complete and an additional technique is presented to improve the quality of the debugging results using multiple interpolants. Experiments on real designs show a 57% reduction in memory and 23% decrease in run-time compared to previous work.
机译：给定错误的设计，功能验证将返回一条错误跟踪，显示出规范与设计实现之间的不匹配。自动化设计调试使用这些错误跟踪来识别导致错误的潜在错误模块。随着现代VLSI设计规模的增加和复杂性的增加，错误迹线变得越来越长且难以分析。同时，设计调试已成为芯片设计周期中最耗费资源的步骤之一。这项工作提出了一种可扩展的，基于SAT的设计调试算法，该算法使用插值法来过度逼近对错误行为进行建模的约束集。该算法通过使用迭代检查的错误跟踪的子部分，将原始问题划分为一系列较小的子问题。通过使用插值法来适当地约束每个子问题的错误行为，这是可能的，从而显着减少了错误跟踪中同时检查的时间范围。所描述的方法被证明是完整的，并且提出了一种附加技术来使用多个插值来提高调试结果的质量。实际设计的实验表明，与以前的工作相比，内存减少了57％，运行时间减少了23％。

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