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首页> 外文会议>Fourth ACM/IEEE International Symposium on Networks-on-Chip >Evaluating Bufferless Flow Control for On-chip Networks
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Evaluating Bufferless Flow Control for On-chip Networks

机译：评估片上网络的无缓冲流控制

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摘要

With the emergence of on-chip networks, the power consumed by router buffers has become a primary concern. Bufferless flow control addresses this issue by removing router buffers, and handles contention by dropping or deflecting flits. This work compares virtual-channel (buffered) and deflection (packet-switched bufferless) flow control. Our evaluation includes optimizations for both schemes: buffered networks use custom SRAM-based buffers and empty buffer bypassing for energy efficiency, while bufferless networks feature a novel routing scheme that reduces average latency by 5%. Results show that unless process constraints lead to excessively costly buffers, the performance, cost and increased complexity of deflection flow control outweigh its potential gains: bufferless designs are only marginally (up to 1.5%) more energy efficient at very light loads, and buffered networks provide lower latency and higher throughput per unit power under most conditions.
机译：随着片上网络的出现，路由器缓冲区所消耗的功率已成为首要问题。无缓冲区流量控制通过删除路由器缓冲区来解决此问题，并通过丢弃或偏移分支来处理争用。这项工作比较了虚拟通道（缓冲）和偏转（分组交换无缓冲）流控制。我们的评估包括针对这两种方案的优化：缓冲网络使用自定义的基于SRAM的缓冲区和空缓冲区旁路以提高能效，而无缓冲网络则采用了新颖的路由方案，可将平均延迟降低5％。结果表明，除非工艺约束导致缓冲器的成本过高，否则偏转流控制的性能，成本和复杂性将超过其潜在收益：在非常轻的负载和缓冲网络下，无缓冲器设计的能源效率仅高一点（高达1.5％）在大多数情况下，提供较低的延迟和较高的每单位功率吞吐量。

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