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On the Mitigation of Cache Hostile Memory Access Patterns on Many-Core CPU Architectures

机译：关于缓解多核CPU架构上的缓存敌对内存访问模式的问题

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Kernels with low arithmetic intensity with memory footprint exceeding cache sizes are typically categorised as memory bandwidth bound. Kernels of this class are typically limited by hardware memory bandwidth. In this work we contribute a simple memory access pattern, derived from a widely-used upwinded stencil-style benchmark, which presents significant challenges for cache-based architectures. The problem appears to grow worse as CPU core counts increase, and the pattern in its initial form shows no benefit from the new high-bandwidth memory now appearing on the Intel Xeon Phi (Knights Landing) family of processors. We describe the memory access scenarios which appear to be causing lower than expected cache performance, before presenting optimisations to mitigate the problem. These optimisations result in useful effective memory bandwidth and runtime improvements by up to 4X on cache based architectures. Results are presented on the Intel Xeon (Broadwell) and Xeon Phi (Knights Landing) processors.

机译：具有较低算术强度且内存占用量超过高速缓存大小的内核通常被归类为内存带宽绑定。此类内核通常受硬件内存带宽的限制。在这项工作中，我们贡献了一种简单的内存访问模式，该模式是从广泛使用的上卷模板样式基准中得出的，这对基于缓存的体系结构提出了重大挑战。随着CPU内核数量的增加，该问题似乎变得更加严重，而且最初形式的模式也没有显示出英特尔至强融核（Knights Landing）系列处理器上现在出现的新高带宽内存没有任何好处。在介绍优化措施以缓解该问题之前，我们描述了内存访问场景，这些场景可能导致缓存性能低于预期。这些优化可在基于缓存的体系结构上带来有效的有效内存带宽和运行时间最多4倍的改进。结果显示在Intel Xeon（Broadwell）和Xeon Phi（Knights Landing）处理器上。

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《High performance computing》|2017年|348-362|共15页
会议地点 Frankfurt(DE)
作者
Tom Deakin; Wayne Gaudin; Simon Mcintosh-Smith;
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作者单位

Department of Computer Science, University of Bristol, Bristol, UK;

UK Atomic Weapons Establishment, Aldermaston, UK;

Department of Computer Science, University of Bristol, Bristol, UK;

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正文语种 eng
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3. Round-trip latency prediction for memory access fairness in mesh-based many-core architectures [J] . Hengzhu Liu, Xiaohui Zhao, Xiaowen Chen, IEICE Electronics Express . 2014,第24期

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4. On the Mitigation of Cache Hostile Memory Access Patterns on Many-Core CPU Architectures [C] . Tom Deakin, Wayne Gaudin, Simon McIntosh-Smith ISC High Performance Conference . 2017

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On the Mitigation of Cache Hostile Memory Access Patterns on Many-Core CPU Architectures

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