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ECL gate array with integrated PLL-based clock recovery and synthesis for high-speed data and telecom a

机译:ECL门阵列,具有基于PLL的集成时钟恢复和综合功能,适用于高速数据和电信

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Abstract: A 2500 gate mixed signal gate array has been developed that integrates custom PLL-based clock recovery and clock synthesis functions with 2500 gates of configurable logic cells to provide a single chip solution for 200 - 1244 MHz fiber based digital interface applications. By customizing the digital logic cells, any of the popular telecom and datacom standards may be implemented. !0
机译:摘要:已开发出2500门混合信号门阵列,该阵列将基于定制PLL的时钟恢复和时钟合成功能与2500个可配置逻辑单元门集成在一起,为基于200-1244 MHz光纤的数字接口应用提供单芯片解决方案。通过定制数字逻辑单元,可以实现任何流行的电信和数据通信标准。 !0

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