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首页> 外文会议>IEEE(Institute of Electrical and Electronics Engineers) International Frequency Control Symposium and Exhibition; 20050829-31; Vancouver(CA) >Phase-Accumulator based Multi-Channel High-Precision Digital PWM Architecture
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Phase-Accumulator based Multi-Channel High-Precision Digital PWM Architecture

机译：基于相位累加器的多通道高精度数字PWM架构

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摘要

A novel fully digital accumulator based pulse-width modulation (PWM) architecture operates in frequency domain, permitting to autonomously control frequency and phase parameters independently without the need for additional processor intelligence, e.g. in real-time time-critical applications. The fully digital design is available in text-based hardware design language (HDL), offering flexibility in technology implementation. High-precision sample implementations include 0.35μm CMOS ASIC, CPLD, and FPGA. For clock rates in excess of 100 MHz, pulse step widths of 10 ns and a digital settability of sub-Hertz and fractions of degrees in frequency and phase resolution are realistic. The architecture allows for cascading an in principle unlimited number of synchronous channels rigid in frequency and phase, subject only to available chip or logic resources. Finally, implemented as ASIC, highest clock rates are conceivable either by quartz, or by an on-chip ring oscillator, with the PWM carrier tuned digitally to an external (lower frequency) reference.
机译：一种新颖的基于全数字累加器的脉宽调制（PWM）体系结构可在频域内运行，从而无需进行额外的处理器智能处理即可独立自主地控制频率和相位参数。在实时，时间紧迫的应用中。全数字化设计可以使用基于文本的硬件设计语言（HDL），从而在技术实施方面提供了灵活性。高精度示例实现包括0.35μmCMOS ASIC，CPLD和FPGA。对于超过100 MHz的时钟速率，切合10 ns的脉冲步长以及亚赫兹的数字可设置性以及频率和相位分辨率的几分之一是切合实际的。该架构允许级联无限数量的频率和相位刚性的同步通道，而仅取决于可用的芯片或逻辑资源。最后，作为ASIC实现，可以通过石英或片上环形振荡器来实现最高时钟速率，同时将PWM载波数字调谐至外部（较低频率）基准。

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