Research on semiconductor wafer fabrication's hot lots problem

机译：半导体晶圆制造热点问题研究

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In this paper the hot lots problem on semiconductor wafer fabrication is studied. Corresponding mathematical model whose object is to minimize the total cost of produce and transport is made. The method based on Binary Particle Swarm Optimization algorithm is proposed to solve this problem. The detailed realization of the method is illustrated,and an example is presented,the simulation results compared to solved by lingo software proves that the BPSO method is effective and stable.

机译：本文研究了半导体晶圆制造中的热点问题。建立了相应的数学模型，其目的是使生产和运输的总成本最小化。为解决该问题，提出了一种基于二进制粒子群优化算法的方法。举例说明了该方法的详细实现，并给出了一个实例，与lingo软件进行的仿真比较表明该方法是有效且稳定的。

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《IEEE international conference on industrial engineering and engineering management;IEEM'2009》|2009年|p.2131-3135|共1005页
会议地点 Beijing(CN);Beijing(CN)
作者
Xu Sheng-liang; Ma Hui-min; Huang Zhong-lin;
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Economic Management School Shanghai Dianji University Shanghai P.R.China;

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关键词
Semiconductor wafer fabrication; Hot lots problem; Binary Particle Swarm Optimization Algorithm;

机译：半导体晶圆制造；热点问题；二进制粒子群优化算法;

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专利

1. Simultaneous order-lot pegging and wafer release planning for semiconductor wafer fabrication facilities [J] . Seung-Kil Lim, Jae-Gon Kim, Hwa-Joong Kim International Journal of Production Research . 2014,第11a12期

机译：半导体晶圆制造设施的同时定单挂料和晶圆发布计划
2. Scheduling Wafer Lots on Diffusion Machines in a Semiconductor Wafer Fabrication Facility [J] . Semiconductor Manufacturing, IEEE Transactions on . 2010,第2期

机译：在半导体晶圆制造工厂中的扩散机上调度晶圆数量
3. A Performance Driven Lot Merging Method with Closed Loop Optimization for Semiconductor Wafer Fabrication [J] . CAO Zhengcai, HUANG Zhexiao, LIU Min 电子学报（英文版） . 2017,第005期

机译：半导体晶片制造的性能驱动批量合并闭环优化方法
4. Research on semiconductor wafer fabrication's hot lots problem [C] . Xu Sheng-liang, Ma Hui-min, Huang Zhong-lin International Conference on Industrial Engineering and Engineering Management . 2009

机译：半导体晶片制造热批量问题的研究
5. Modeling and control of wiresaw and lapping processes in semiconductor wafer fabrication. [D] . Zhu, Liqun. 2004

机译：半导体晶圆制造中线锯和研磨工艺的建模和控制。
6. Fabrication of Si/graphene/Si Double Heterostructures by Semiconductor Wafer Bonding towards Future Applications in Optoelectronics [O] . Takenori Naito, Katsuaki Tanabe 2018

机译：半导体晶圆键合技术在硅/石墨烯/硅双异质结构的制备中的应用
7. INTELLIGENT SIMULATION-BASED LOT SCHEDULING OF PHOTOLITHOGRAPHY TOOLSETS IN A WAFER FABRICATION FACILITY [O] . R G. Ingalls, M. D. Rossetti, J. S. Smith, 2009

机译：晶圆制造设施中基于智能模拟的照相光刻工具批量调度
8. Semiconductor Measurement Technology: Evaluating a Chip, Wafer, or Lot Using SUXES, SPICE, and STAT2. [R] . Marshall, J. C., Mattis, R. L. 1992

机译：半导体测量技术：使用sUXEs，spICE和sTaT2评估芯片，晶圆或批次。

Research on semiconductor wafer fabrication's hot lots problem

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