Design of configurable power efficient 2-dimensional crossbar switch for network-on-chip(NoC)

机译：片上网络（NoC）的可配置高效节能二维交叉开关设计

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Network-on-Chip is an emerging paradigm for integrating very high number of Intellectual Property blocks on a single Integrated Chip. In this paper, crossbar switch is designed for 2-D Mesh Network-on-Chip to meet the current requirements of high speed networks. The design reduced the power consumption significantly and can meet the scalable bandwidth. The functional verification of the crossbar switch design using ModelSim 6.4a has been shown. Synthesis has been performed on Xilinx 13.3 and it is verified using FPGA.

机译：片上网络是一种新兴的范例，用于在单个集成芯片上集成大量知识产权模块。在本文中，交叉开关是为2-D Mesh片上网络设计的，可以满足当前高速网络的需求。该设计显着降低了功耗，并且可以满足可扩展带宽。已经显示了使用ModelSim 6.4a对纵横开关设计进行功能验证。综合已经在Xilinx 13.3上执行，并且已使用FPGA进行了验证。

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来源
《IEEE International Conference on Recent Trends In Electronics Information Communication Technology》|2016年|1514-1517|共4页
会议地点 Bengaluru(IN)
作者
Shilpi Bansal; Satyendra Sharma; Nidhi Sharma;
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作者单位

Electronics and Communication Engg. NIET, Greater Noida, India;

Electronics and Communication Engg., NIET, Greater Noida, India;

Electronics and Communication Engg., NIET, Greater Noida, India;

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原文格式 PDF
正文语种 eng
中图分类
关键词
Switches; Computer architecture; Ports (Computers); Network-on-chip; Bandwidth;

机译：交换机;计算机体系结构;端口（计算机）;片上网络;带宽;

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专利

1. Design of a performance enhanced and power reduced dual-crossbar Network-on-Chip (NoC) architecture [J] . Yixuan Zhang, Randy Morris, Avinash K. Kodi Microprocessors and microsystems . 2011,第2期

机译：性能增强和功耗降低的双交叉开关片上网络（NoC）架构的设计
2. Design of an Area-Efficient and Low-Power Hierarchical NoC Architecture Based on Circuit Switching [J] . Woo Joo Kim, Sung Hee Lee, Sun Young Hwang IEICE Transactions on fundamentals of electronics, communications & computer sciences . 2009,第3期

机译：基于电路交换的高效低功耗分层NoC架构设计
3. Self-Reconfigurable Channel Data Buffering Scheme and Circuit Design for Adaptive Flow Control in Power-Efficient Network-on-Chips [J] . Bondade R., Ma D. Circuits and Systems I: Regular Papers, IEEE Transactions on . 2010,第11期

机译：高效节能片上网络中自适应流量控制的自重配置通道数据缓冲方案和电路设计
4. Design of Configurable Power Efficient 2-Dimensional Crossbar Switch For Network-on-Chip(NoC) [C] . Shilpi Bansal, Satyendra Sharma, Nidhi Sharma IEEE International Conference on Recent Trends in Electronics, Information Communication Technology . 2016

机译：网络上网（NOC）可配置功率有效二维交叉开关的设计
5. Design of high-performance, energy-efficient, and reliable Network-on-Chip (NoC) architectures. [D] . Park, Dongkook. 2008

机译：高性能，高能效，可靠的片上网络（NoC）架构的设计。
6. Partial-Gated Memristor Crossbar for Fast and Power-Efficient Defect-Tolerant Training [O] . Khoa Van Pham, Tien Van Nguyen, Kyeong-Sik Min 2019

机译：局部门忆阻器交叉开关可进行快速高效的耐缺陷培训
7. Adaptive Inter-router Links for Low-Power, Area-Efficient and Reliable Network-on-Chip (NoC) Architectures [O] . 2014

机译：适用于低功耗，面积有效且可靠的片上网络（NoC）架构的自适应路由器间链路

Design of configurable power efficient 2-dimensional crossbar switch for network-on-chip(NoC)

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