A compact, low power AES core on 180nm CMOS process

机译：采用180nm CMOS工艺的紧凑型低功耗AES内核

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This paper presents a compact, low power AES cryptography core with a small S-box and an improved key expansion block for emerging wireless networks. The implementation results with an 180nm CMOS standard library show that the proposed AES core can reduce the area and power consumption significantly.

机译：本文提出了一个紧凑的，低功耗的AES加密核心，带有一个小型S-box和一个针对新兴无线网络的改进的密钥扩展模块。 180nm CMOS标准库的实现结果表明，所提出的AES内核可以显着减少面积和功耗。

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来源
《IEEE Joint Conference: International Conference on IC Design and Technology amp; Solid State Systems Symposium》|2016年|1-5|共5页
会议地点 Ho Chi Minh City(VN)
作者
Van-Lan Dao; Van-Phuc Hoang; Anh-Thai Nguyen; Quy-Minh Le;
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作者单位

Le Quy Don Technical University, 236 Hoang Quoc Viet Str., Hanoi, Vietnam;

Le Quy Don Technical University, 236 Hoang Quoc Viet Str., Hanoi, Vietnam;

Le Quy Don Technical University, 236 Hoang Quoc Viet Str., Hanoi, Vietnam;

Le Quy Don Technical University, 236 Hoang Quoc Viet Str., Hanoi, Vietnam;

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会议组织
原文格式 PDF
正文语种 eng
中图分类
关键词
Encryption; Wireless networks; Semiconductor device modeling; CMOS integrated circuits; Standards; Hardware;

机译：加密;无线网络;半导体器件建模; CMOS集成电路;标准;硬件;

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1. Design of ultra-low power AES encryption cores with silicon demonstration in SOTB CMOS process [J] . V.-P. Hoang, V.-L. Dao, C.-K. Pham Electronics Letters . 2017,第23期

机译：SOTB CMOS工艺中的硅演示设计超低功耗AES加密内核
2. Low-power compact composite field AES S-Box/Inv S-Box design in 65 nm CMOS using Novel XOR Gate [J] . Nabihah Ahmad, S.M. Rezaul Hasan Integration . 2013,第4期

机译：使用新型XOR门的65 nm CMOS低功耗紧凑型复合场AES S-Box / Inv S-Box设计
3. Design of a Low Voltage low Power Double tail comparator in 180nm cmos Technology [J] . Mr. Deepak Joseph Babu, Mr. Sunil Jacob American Journal of Engineering Research . 2014,第9期

机译：采用180nm CMOS技术的低压低功耗双尾比较器的设计
4. A compact, low power AES core on 180nm CMOS process [C] . Van-Lan Dao, Van-Phuc Hoang, Anh-Thai Nguyen, Solid State Systems Symposium . 2016

机译：180nm CMOS工艺的紧凑型低功耗AES核心
5. High-Performance, Low-Power, and Compact CMOS VLSI Circuits with Carbon Nanotube Transistor Technology [D] . Sun, Yanan. 2014

机译：具有碳纳米管晶体管技术的高性能，低功耗和紧凑型CMOS VLSI电路
6. Design of a MEMS-Based Oscillator Using 180nm CMOS Technology [O] . Sukanta Roy, Harikrishnan Ramiah, Ahmed Wasif Reza, -1

机译：基于180nm CMOS技术的基于MEMS的振荡器设计
7. Design and Simulation of Low Power CMOS Adder Cell at 180nm using Tanner Tool [O] . Chakshu Goel, Puneet Jain, Gurjeevan Singh 2016

机译：用Tanner工具设计和模拟180nm低功率CmOs加法器单元

A compact, low power AES core on 180nm CMOS process

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