• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文会议>IEEE Joint Conference: International Conference on IC Design and Technology amp; Solid State Systems Symposium >Ultra low-power and low-energy 32-bit datapath AES architecture for IoT applications
【24h】

Ultra low-power and low-energy 32-bit datapath AES architecture for IoT applications

机译：适用于IoT应用的超低功耗和低能耗32位数据路径AES架构

获取原文
获取原文并翻译 | 示例
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

In this paper, we propose a novel AES microarchitecture with 32-bit datapath optimized for low-power and low-energy consumption targeting IoT applications. The proposed design uses simple shift registers for key/data storage and permutation to minimize the area, and the power/energy consumption. These shift registers also minimize the control logics in the key expansion and the encryption path. The proposed architecture is further optimized for area and/or power/energy consumption by selecting a suitable implementation of S-boxes and applying the clock gating technique. The implementation results in TSMC 65nm technology show that our design can save 20% of area or 20% of energy per bit at the same area when compared with the current 32-bit datapath designs. Our design also occupies smaller core area with lower energy per bit and at least 4 times higher in throughput in comparison with other 8-bit designs in the same technology node.
机译：在本文中，我们提出了一种针对32位数据路径的新型AES微体系结构，该体系结构针对针对物联网应用的低功耗和低能耗进行了优化。提出的设计使用简单的移位寄存器进行键/数据存储和置换，以最大程度地减小面积和功耗/能耗。这些移位寄存器还使密钥扩展和加密路径中的控制逻辑最小化。通过选择合适的S盒实现并应用时钟门控技术，可以进一步针对面积和/或功耗/能耗优化所提出的架构。台积电65纳米技术的实施结果表明，与当前的32位数据路径设计相比，我们的设计可在同一面积上节省20％的面积或每位节省20％的能量。与同一个技术节点中的其他8位设计相比，我们的设计还占用了较小的核心区域，每位能耗更低，吞吐量至少高出4倍。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号