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首页> 外文会议>IMAPS 2008 - 41st international symposium on microelectronics: bringing together the entire microelectronics supply chain >Low-k Interconnect Oriented Lead Free Sn-Cu Bump Process Integration with Sn/Cu Stack Plating
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Low-k Interconnect Oriented Lead Free Sn-Cu Bump Process Integration with Sn/Cu Stack Plating

机译：面向低k互连的无铅Sn-Cu凸点工艺集成与Sn / Cu堆叠镀层

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摘要

We have developed Low-k oriented lead free Sn-Cu bump process integration with Sn/Cu stack plating. The key features are lower cost process than alloy plating, by sequential plating pure Cu and pure Sn, and suitable for low-k interconnects, with Sn-Cu bump material has high potential of stress alleviation effect. Sn-Cu bump employed sequential Cu and Sn electroplating followed flux reflows. We have found wide process latitude depended on stacked thickness ratio of Cu/Sn. Single metal plating process combination with Cu and Sn has a cost advantage. Thin Ni barrier layer thickness has achieved only 350nm with sputtering. The reliability test shows superior results of TCT B (Thermal cycle test), PCT, and HTS reliability test with low-k material interconnection, which use k=2.7 material. Sn-Cu bump has a high creep rate, therefore Su-Cu deformed itself and alleviated the stress of thermal cycle for low-k interconnects. EM test also shows sufficient for application.rnThus, the lead free SnCu bump has a potential of most suitable candidate of low-k BEOL 65 nm and more shrinkage generation which has weaker mechanical property and greater die size.
机译：我们已经开发了低k取向的无铅Sn-Cu凸点工艺与Sn / Cu叠层电镀集成。其主要特点是与合金镀相比，通过依次镀纯Cu和纯Sn可以降低成本，并且适用于低k互连，而Sn-Cu凸点材料具有缓解应力的潜力。 Sn-Cu凸块采用顺序Cu和Sn电镀，然后进行助焊剂回流。我们发现宽的工艺范围取决于Cu / Sn的堆叠厚度比。与Cu和Sn的单金属电镀工艺组合具有成本优势。溅射时，薄的镍阻挡层厚度仅达到350nm。可靠性测试显示，使用k = 2.7材料的低k材料互连的TCT B（热循环测试），PCT和HTS可靠性测试具有优异的结果。 Sn-Cu凸块具有较高的蠕变速率，因此Su-Cu自身变形并减轻了低k互连的热循环应力。 EM测试也显示出足够的应用前景。因此，无铅SnCu凸点具有最适合低k BEOL 65 nm的潜力，并且产生的收缩率更大，机械性能较弱且管芯尺寸更大。

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