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The Effect of Package Pin Map on Signal Integrity for Test Applications

机译:封装引脚图对测试应用中信号完整性的影响

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In the past decade the increasing signal speed of IC circuits has made the packaging design more challenging than ever. In order to deliver the signals from chip to PCB with minimal distortions,the signal integrity analysis has become a critical step of package design. Modern SI analysis tools have made it possible to analyze both package and PCB for signal integrity performance in order to achieve first pass system design success with ever-shrinking margins. However,the test socket has been mostly left out of such workflows of signal integrity analysis. The IC test engineers have been constantly challenged to develop test solutions where the system budget for the test sockets is rarely considered at design time. This paper examines the effects of package pin map on the signal integrity performance of the IC-socket-PCB system based on some real world case studies. The results clearly demonstrate that by including the socket into the system level design,the signal integrity performance of the package-socket-PCB system can be greatly improved. The paper also discusses the relationship between bandwidth,inductance,impedance and contact length.
机译:在过去的十年中,IC电路不断提高的信号速度使封装设计比以往更具挑战性。为了以最小的失真将信号从芯片传递到PCB,信号完整性分析已成为封装设计的关键步骤。现代化的SI分析工具使分析封装和PCB的信号完整性性能成为可能,从而以最小的裕度实现了首过系统设计的成功。但是,测试插座大多数都没有进行信号完整性分析这样的工作流程。 IC测试工程师一直面临开发测试解决方案的挑战,而在设计时很少考虑测试插座的系统预算。本文基于一些实际案例研究了封装引脚图对IC-socket-PCB系统信号完整性性能的影响。结果清楚地表明,通过将插座包含在系统级设计中,可以大大提高封装插座PCB系统的信号完整性。本文还讨论了带宽,电感,阻抗和接触长度之间的关系。

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