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Cooling High Power Devices and Systems: State of the Art and the Inevitable Future Cooling Alternatives

机译:冷却大功率设备和系统:最先进的技术和未来不可避免的冷却选择

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In the last decade, the microprocessor power dissipation has gone up by a factor of ten. The frequency of operation of CMOS devices has increased ten fold. While the input voltage and capacitance of devices has decreased, the number of devices on a typical microprocessor die has increased by an order of magnitude. Moreover, device miniaturization has led to integration of cache contained at a multi-chip level to one contained on the microprocessor die. This has resulted in high CPU core power density -e.g. 50% of a 20 mm by 20 mm micro-processor die may contain the CPU core, with the rest being cache. The total power dissipation from such a microprocessor has reached 100 W, and the power density is estimated to be 40 W/cm~2. Extrapolating the changes in microprocessor organization and the device miniaturization, one can project future power dissipation of 100 W from a 1 cm by 1 cm core CPU surface area. As multiple CPU cores become the norm, a power dissipation of 50 W from a 5 mm by 5 mm core will result in power density of 200 W/cm~2! This increase in total power, and to a greater extent the power density, has resulted in the need for very low thermal resistance cooling solutions at device and system level. The system power, especially the high and mid range computer servers, has undergone similar increase, in the high compute density data centers, populated with rack mounted slim servers, one can pack 10 KW of power in a standard rack. The data center itself begins to look like a computer or an auditorium with 100 people per seat. This talk will focus in the following key areas: 1. Power dissipation trends and quantification of cooling solution targets I.e. The thermal resistance target sought for the overall cooling solution. 2. Current cooling solutions for 100 W microprocessors with power density in the 40 W/cm~2 range. 3. Cooling Alternatives for Future Devices & Systems; 4. Data Center Power Issues.
机译:在过去的十年中,微处理器的功耗增加了十倍。 CMOS器件的工作频率增加了十倍。当设备的输入电压和电容降低时,典型微处理器芯片上的设备数量增加了一个数量级。此外,设备的小型化导致将多芯片级包含的高速缓存集成到微处理器裸片中包含的高速缓存中。这导致了很高的CPU内核功率密度-例如20毫米x 20毫米微处理器裸片的50%可能包含CPU内核,其余的则被缓存。这种微处理器的总功耗已达到100 W,并且功率密度估计为40 W / cm〜2。通过对微处理器组织和设备小型化的变化进行推断,可以预测从1 cm x 1 cm核心CPU表面积获得的100 W未来功耗。随着多个CPU内核成为常态,从5毫米乘5毫米内核消耗50瓦功率将导致200 W / cm〜2的功率密度!总功率的增加以及更大程度地功率密度的增加,导致需要在设备和系统级别上非常低的热阻冷却解决方案。在高计算密度的数据中心中,系统功率(尤其是中高端计算机服务器)经历了类似的增长,在装有机架式瘦服务器的高计算密度数据中心中,一台标准机架中可以容纳10 KW功率。数据中心本身开始看起来像一台计算机或礼堂,每个席位可容纳100人。演讲将集中在以下关键领域:1.功耗趋势和冷却解决方案目标的量化,即热阻目标寻求整体冷却解决方案。 2.当前功率为40 W / cm〜2的100 W微处理器的冷却解决方案。 3.未来设备和系统的散热方案; 4.数据中心电源问题。

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