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Parallel and Pipeline Processing for Block Cipher Algorithms on a Network-on-Chip

机译:片上网络中分组密码算法的并行和流水线处理

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The computational performance of network-on-chip (NoC) and multi-processor system-on-chip (MPSoC) for implementing cryptographic block ciphers can be improved by exploiting parallel and pipeline execution. In this paper, we present a parallel and pipeline processing method for block cipher algorithms: data encryption standard (DES), triple-DES Algorithm (TDEA), and advanced encryption standard (AES) based on pure software implementation on an NoC. The algorithms are decomposed into task loops, functions, and data flow for parallel and pipeline execution. The tasks are allocated by the proposed mapping strategy to each processing element (PE) which consists of a 32-bit reduced instruction set computer (RISC) core, internal memory, router, and Network Interface (NI) to communicate between PEs. The proposed approach is simulated by using networked processor array (NePA), the cycle-accurate SystemC and hardware description language (HDL) model platform. We show that our method has the advantage of flexibility as compared to previous implementations of cryptographic algorithms based on hardware and software co-design or traditional hardwired ASIC design. In addition, the simulation result presents that the parallel and pipeline processing approach for software block ciphers can be implemented on various NoC platforms which have different complexities and constraints.
机译:可以通过利用并行和流水线执行来提高用于实现密码分组密码的片上网络(NoC)和多处理器片上系统(MPSoC)的计算性能。在本文中,我们提出了一种基于NoC的纯软件实现的分组密码算法的并行和流水线处理方法:数据加密标准(DES),三重DES算法(TDEA)和高级加密标准(AES)。这些算法被分解为任务循环,功能和数据流,以并行和流水线执行。所提出的映射策略将任务分配给每个处理元素(PE),每个处理元素由32位精简指令集计算机(RISC)内核,内部存储器,路由器和网络接口(NI)组成,以在PE之间进行通信。通过使用网络处理器阵列(NePA),周期精确的SystemC和硬件描述语言(HDL)模型平台对所提出的方法进行了仿真。我们证明,与以前基于硬件和软件协同设计或传统硬线ASIC设计的密码算法实现相比,我们的方法具有灵活性的优势。此外,仿真结果表明,可以在具有不同复杂性和约束条件的各种NoC平台上实现软件块密码的并行和流水线处理方法。

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