Dept. of Electr. Eng. Comput. Sci., Univ. of California, Irvine, Irvine, CA;
cryptography; electronic engineering computing; hardware description languages; network-on-chip; parallel processing; pipeline processing; reduced instruction set computing; MPSoC; NoC; advanced encryption standard; cryptographic block cipher; cycle-accurate SystemC; data encryption standard; hardware description language; multiprocessor system-on-chip; networked processor array; tripleDES algorithm; block cipher; parallel and pipeline processing; security; software implementation;
机译:基于GPU的并行处理轻量块密码的微分分布分析
机译:基于CPU-GPU的并行搜索算法,用于块密码的最佳差分特性
机译:具有可重配置流水线总线系统的线性阵列上的快速且处理器高效的并行矩阵乘法算法
机译:网络上块密码算法的平行和管道处理
机译:parallel_dp:并行动态编程设计模式,它是IntelRTM线程构建模块算法模板。
机译:affyPara-用于Affymetrix芯片数据的并行预处理算法的生物导体包装
机译:片上网络分组密码算法的并行和流水线处理