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首页> 外文会议>International Conference and Workshops on Recent Advances and Innovations in Engineering >MDAB: Module Design Automation Block for Verification using System Verilog Testbench
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MDAB: Module Design Automation Block for Verification using System Verilog Testbench

机译：MDAB：使用系统Verilog Testbench进行验证的模块设计自动化模块

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摘要

Verification is the process of testing various design scenarios using different test cases. The verification process consists of multiple phases in hierarchical order including random verification, coverage collection, register abstraction and power verification. The unautomated Verilog environments acquire the testbench and design in separate modules. It is highly susceptible to errors due to race around condition between design and testbench. A System Verilog synthesizable constructor testbench environment brings program block to initialize free and fast working of the testbench. The proposed testbench facilitates self-checking assertion-based verification for automatic design database generation to reduce verification time drastically. The testbench run is designed in co-simulation wizard of the python script. The script works for validation and data extraction from the design shell. The verification process consumes the majority of time in design development life cycle. The paper contributes to reducing the simulation time and process time as compared to unautomated Verilog and system C test benches. The design-verification must acquire more than 90 % successful consequences before tape-out.
机译：验证是使用不同的测试用例测试各种设计方案的过程。验证过程由分层顺序的多个阶段组成，包括随机验证，覆盖范围收集，寄存器抽象和功率验证。非自动化的Verilog环境在单独的模块中获得测试平台和设计。由于设计和测试台之间的竞争，它极易出错。 System Verilog可综合构造器测试平台环境带来了程序块，以初始化测试平台的自由和快速工作。拟议的测试平台有助于自动设计数据库生成的基于自检声明的验证，从而大大减少了验证时间。 testbench运行是在python脚本的协同仿真向导中设计的。该脚本可用于从设计外壳进行验证和数据提取。验证过程会消耗设计开发生命周期中的大部分时间。与非自动Verilog和系统C测试台相比，本文有助于减少仿真时间和处理时间。在进行流片之前，设计验证必须获得90％以上的成功结果。

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