Fault Tolerant Architecture Design of a 4-bit Magnitude Comparator

机译：4位幅度比较器的容错体系结构设计

获取原文

页面导航

摘要
著录项
相似文献
相关主题

摘要

This paper provides a detailed explanation of a fault tolerant method to provide uninterrupted operation in a magnitude comparator based system. Fault may manifest in an electronic system either by virtue of external or internal factors. The following structure provides a subtle way to minimize those factors and make a 4-bit fault tolerant magnitude comparator so that it can reconfigure itself automatically. Area overheard, delay and cost efficiency of our proposed method is compared to that of Triple Modular Redundancy's.

机译：本文详细介绍了在基于幅值比较器的系统中提供不间断操作的容错方法。故障可能会由于外部或内部因素而在电子系统中显现出来。以下结构提供了一种微妙的方法，可将这些因素降至最低，并制作一个4位容错幅度比较器，使其可以自动重新配置。将我们提出的方法的面积窃听，延迟和成本效率与三重模块冗余的方法进行了比较。

著录项

来源
《International Conference on Computer, Electrical Communication Engineering》|2017年|1-6|共6页
会议地点 Kolkata(IN)
作者
Priti Das; Apurva Sinha; Atin Mukherjee;
展开▼
作者单位

Department of Electronics and Communication Techno India University Kolkata India;

展开▼
会议组织
原文格式 PDF
正文语种
中图分类
关键词
Very large scale integration; Circuit synthesis; Test pattern generators; Fault detection;

机译：超大规模集成；电路综合；测试码型发生器；故障检测;

相似文献

外文文献
中文文献
专利

1. Strategic Planning for Fault-Tolerant Internet Connectivity Using Basic Fault-Tolerant Architectural Design as Platform [J] . O.O. Adeosun, E.R. Adagunodo, I.A. Adetunde, Asian Journal of Scientific Research . 2008,第2期

机译：以基本的容错体系结构设计为平台的容错Internet连接的战略规划
2. A 4-BIT EXPANDABLE CURRENT-MODE ADC BASED ON DIFFERENT CURRENT COMPARATOR ARCHITECTURES [J] . VEEPSA BHATIA, NEETA PANDEY, ASOK BHATTACHARYYA International Journal of Engineering Science and Technology . 2010,第12期

机译：基于不同电流比较器架构的4位可扩展电流模式ADC
3. Design of power efficient, high-speed 4-bit comparator in UMC 180 nm technology [J] . Sudheer Raja Venishetty, Anil Kumar Chidra Engineering and Applied Science Research . 2021,第1期

机译：UMC 180 NM技术中功率高效，高速4位比较器的设计
4. Fault Tolerant Architecture Design of a 4-bit Magnitude Comparator [C] . Priti Das, Apurva Sinha, Atin Mukherjee International Conference on Computer, Electrical amp;amp;amp; Communication Engineering . 2017

机译：4位幅度比较器的容错架构设计
5. Design and Development of Reliable and Fault-Tolerant Network-on-Chip Router Architecture. [D] . Alhussien, Abdulaziz. 2013

机译：可靠且容错的片上网络路由器体系结构的设计和开发。
6. Fault-Tolerant Network-On-Chip Router Architecture Design for Heterogeneous Computing Systems in the Context of Internet of Things [O] . Muhammad Rashid, Naveed Khan Baloch, Muhammad Akmal Shafique, 2020

机译：容错网络上环路路由器架构在内容互联网上的异构计算系统
7. Design and Simulation of BIST based 4-Bit Binary Comparator based on Reversible Logic Architecture [O] . Manish Kumar, Braj Bihari 2016

机译：基于可逆逻辑架构的基于BIST的4位二进制比较器的设计与仿真
8. Advanced information processing system: The Army fault tolerant architecture conceptual study. Volume 2: Army fault tolerant architecture design and analysis [R] . Harper, R. E., Alger, L. S., Babikyan, C. A., 1992

机译：先进的信息处理系统：陆军容错架构概念研究。第2卷：陆军容错架构设计和分析

Fault Tolerant Architecture Design of a 4-bit Magnitude Comparator

摘要

著录项

相似文献

相关主题

期刊订阅