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An FPGA-based incremental encoder signal conditioner with reduced error in rotational rate estimation over a wide range of rotational speeds

机译:基于FPGA的增量式编码器信号调节器,可在较宽的转速范围内降低转速估算误差

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Digital motion controllers (DMC) usually employ incremental encoders (IE) as angular position sensors and deploy one out of a handful of candidate algorithms to estimate the rotational rate from the pulse counts obtained from the IE at a periodic rate. The electronics for signal conditioning of the IE output pulse trains, elimination of input glitches and pulse multiplier for resolution enhancement are well-established hardware and all state-of-the-art DMCs have on-chip module of the same. The rate estimation algorithms based on the encoder pulse counts, however, tend to become erroneous at low rotational speeds. This problem is usually circumvented by a reciprocal counting mechanism, where the time between two successive IE pulses is measured to estimate the rotational rate. This paper proposes a seamless switching protocol between the two rate computing methods and presents the design of an Incremental Encoder Signal Conditioner (IESC) and its FPGA-based implementation that embeds the direct and reciprocal rate computation algorithms along with the automated changeover mechanism between the two for a more accurate estimation of rotational speed in a wide range of rotational speeds. The paper also presents the performance of the IESC over a large range of rotational rates.
机译:数字运动控制器(DMC)通常采用增量编码器(IE)作为角位置传感器,并部署少数几种候选算法中的一种,以周期性地从从IE获得的脉冲计数中估算旋转速率。用于IE输出脉冲序列的信号调理,消除输入毛刺和用于提高分辨率的脉冲倍增器的电子设备是公认的硬件,并且所有最新的DMC都具有相同的片上模块。但是,基于编码器脉冲计数的速率估计算法在低转速下会变得错误。通常通过往复计数机制来避免此问题,在该机制中,要测量两个连续的IE脉冲之间的时间以估算转速。本文提出了两种速率计算方法之间的无缝切换协议,并提出了增量编码器信号调节器(IESC)的设计及其基于FPGA的实现,该实现将直接速率和倒数速率计算算法以及两者之间的自动转换机制嵌入其中用于在较宽的转速范围内更准确地估算转速。本文还介绍了IESC在大范围转速下的性能。

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