Performance comparison of various CMOS full adders

机译：各种CMOS全加器的性能比较

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摘要

In this paper a low complexity full adder is proposed. 1-bit full adders perform addition among 3 input bits and give sum and carry outputs. In VLSI circuits, such as video processing, digital signal processing, and microprocessors uses arithmetic operations which are performed by full adder. Full adder is the fundamental block of enhancing the overall performance of the processors. In this paper, a low complexity full adder with 10 transistors hybrid adder featuring level restoring, high computing speed and low energy consumption is proposed. Simulation is carried at 130nm technology using mentor graphics tool. The result is compared with 14 transistors, 10 transistors full adder.

机译：本文提出了一种低复杂度的全加法器。 1位全加法器在3个输入位之间执行加法运算，然后求和并进行输出。在VLSI电路中，例如视频处理，数字信号处理和微处理器使用由全加器执行的算术运算。全加器是增强处理器整体性能的基本要素。本文提出了一种具有电平恢复，高运算速度和低能耗的低复杂度全加法器与十个晶体管混合加法器。使用指导者图形工具以130nm技术进行仿真。将结果与14个晶体管，10个晶体管全加器进行比较。

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来源
《International Conference on Energy, Communication, Data Analytics and Soft Computing》|2017年|3789-3792|共4页
会议地点 Chennai(IN)
作者
Basavoju Harish; K. Sivani; M.S.S. Rukmini;
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作者单位

Dept. of ECE VLITS Guntur India;

Dept. of ECE KITS Warangal Warangal India;

Dept. of ECE VFSTR University Guntur India;

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Adders; Transistors; Logic gates; Power dissipation; Propagation delay; Switching circuits; Very large scale integration;

机译：加法器；晶体管；逻辑门功耗;传播延迟；开关电路；大规模整合;

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1. DESIGN OF LOW POWER REDUCED WALLACE MULTIPLIER WITH COMPACT CARRY SELECT ADDER, HALF ADDER & FULL ADDER USING CMOS TECHNOLOGY [J] . P.RADHIKA, Dr.T.VIGNESWARAN Journal of Theoretical and Applied Information Technology . 2015,第2期

机译：采用CMOS技术的紧凑型随身加法器，半加法器和全加法器的低功耗减薄壁乘法器的设计
2. Power Comparison of CMOS and Adiabatic Full Adder Circuits [J] . Y. Sunil Gavaskar Reddy, V.V.G.S.Rajendra Prasad International Journal of VLSI Design & Communication Systems . 2011,第3期

机译：CMOS和绝热全加器电路的功率比较
3. LAHAF: Low-power, area-efficient, and high-performance approximate full adder based on static CMOS [J] . Fatemieh Seyed Erfan, Farahani Samira Shirinabadi, Reshadinezhad Mohammad Reza Sustainable Computing . 2021,第Juna期

机译：Lahaf：基于静态CMOS的低功耗，面积效率，高性能近似全加法器
4. Study of Performance Comparison of Static and Dynamic Approximate Reverse Carry Propagate Adder Using 22 nm CMOS Technology [C] . Sedhumadhavan. A, Sabariesh. S, Shanmathi. V, International Conference on Advanced Computing and Communication Systems . 2020

机译：采用22 nm CMOS技术的静态和动态近似反向传播传播加法器性能比较研究
5. Performance tradeoffs of wide-bit CMOS nanometer adder topologies with applied leakage reduction techniques. [D] . Romo, Claudia. 2010

机译：宽比特CMOS纳米加法器拓扑与应用的泄漏减少技术之间的性能折衷。
6. Experimental Comparison of the High-Speed Imaging Performance of an EM-CCD and sCMOS Camera in a Dynamic Live-Cell Imaging Test Case [O] . Hope T. Beier, Bennett L. Ibey -1

机译：动态活细胞成像测试案例中EM-CCD和sCMOS相机高速成像性能的实验比较
7. POWER COMPARISON OF CMOS AND ADIABATIC FULL ADDER CIRCUITS [O] . Y. Sunil Gavaskar Reddy, V.V.G.S.Rajendra Prasad 2011

机译：CmOs与绝极全馈电路的功率比较

Performance comparison of various CMOS full adders

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