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Reducing power consumption for system on programmable chip by scheduling tasks

机译:通过调度任务减少可编程芯片上系统的功耗

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Reducing power consumption has become a main objective in the System on Programmable Chip design. Indeed, increasing integration rates and clock frequencies, it becomes necessary to design techniques to reduce power consumption. These techniques are interesting to satisfy the criteria of autonomy, reliability and cost for embedded systems. In this context, we propose an algorithm to schedule tasks obtained from a hardware/software partitioning and running in parallel. In fact, we reduce their operating frequency tasks in an affordable limit to decrease dynamic power consumption without increasing the overall time execution of the application.
机译:降低功耗已成为可编程芯片系统设计的主要目标。实际上,随着集成速率和时钟频率的提高,有必要设计降低功耗的技术。这些技术对于满足嵌入式系统的自治性,可靠性和成本标准很有趣。在这种情况下,我们提出了一种算法,用于调度从硬件/软件分区获得的并并行运行的任务。实际上,我们在负担得起的范围内减少了它们的工作频率任务,以减少动态功耗,而又不增加应用程序的整体执行时间。

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