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On the Reconfiguration Algorithm for Fault-Tolerant VLSI Arrays

机译:容错VLSI阵列的重新配置算法

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摘要

In this paper, an improved algorithm is presented for the NP-complete problem of reconfiguring a two-dimensional degradable VLSI array under the row and column routing constraints. The proposed algorithm adopts the partial computing for the logical row exclusion so that the most efficient algorithm, cited in literature, is speeded up without loss of performance. In addition, a flaw in the earlier approach is also addressed. Experimental results show that our algorithm is approximately 50% faster than the above stated algorithm.
机译:本文针对行和列路由约束条件下重构二维可降解VLSI阵列的NP-完全问题,提出了一种改进的算法。所提出的算法对逻辑行排除采用部分计算,以便在不损失性能的情况下加快文献中引用的最有效算法。另外,还解决了早期方法中的缺陷。实验结果表明,我们的算法比上述算法快约50%。

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