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首页> 外文会议>International Conference on Cybernetics and Information Technologies, Systems and Applications(CITSA2004) and 10th International Conference on Information Systems Analysis and Synthesis(ISAS2004) vol.3 >Low Power Scheduling for Low Power Systems
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Low Power Scheduling for Low Power Systems

机译：低功耗系统的低功耗调度

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摘要

This paper presents a latency-constrained scheduling algorithm that minimizes power consumption for the resources and registers operating at multiple cycles and voltages (5V, 3.3V, 2.4V, 2.2V, 1.8V, 1.5V, 1.2V, 1V). The proposed schemes are based on the consideration of assigning most nodes to low voltage and reducing the number of registers simultaneously. We present a comprehensive scheduling methodology to decrease average power, peak power, and the number of registers during scheduling stage. To target this goal, we present an efficient algorithm to obtain the near-optimal scheduled DFG with the least power dissipation that satisfies the system constraints in timing. Our benchmark shows that our approach has succeeded to reduce power in 12.99%～41.97% for those multi-media kernels.
机译：本文提出了一种受延迟限制的调度算法，该算法可将资源和寄存器在多个周期和多个电压（5V，3.3V，2.4V，2.2V，1.8V，1.5V，1.2V，1V）下的功耗降至最低。提出的方案是基于将大多数节点分配给低压并同时减少寄存器数量的考虑。我们提出了一种全面的调度方法，可降低调度阶段的平均功率，峰值功率和寄存器数量。为了实现这一目标，我们提出了一种高效的算法，可以以最小的功耗获得满足时间要求的系统约束的接近最优的调度DFG。我们的基准测试表明，对于那些多媒体内核，我们的方法成功地将功耗降低了12.99％〜41.97％。

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