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首页> 外文会议>International Conference on Embedded Software and Systems(ICESS 2005); 20051216-18; Xi'an(CN) >Realization of Video Object Plane Decoder on On-Chip Network Architecture
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Realization of Video Object Plane Decoder on On-Chip Network Architecture

机译：片上网络架构上视频目标平面解码器的实现

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摘要

System-on-chip (SoC) designs provide integrated solutions to challenging design problems in the telecommunications, multimedia, and so on. Present and future SoC are designed using pre-existing components which we call cores. Communication between the cores will become a major bottleneck for system performance as standard hardwired bus-based communication architectures will be inefficient in terms of throughput, latency and power consumption. To solve this problem, a packet switched platform that considers the delay and reliability issues of wires so called Network-on-Chip (NoC) has been proposed. In this paper, we present interconnected network topologies and analyze their performances with a particular application under bandwidth constrains. Then we compare the performances among different ways of mapping the cores onto a Mesh NoC architecture. The comparison between Mesh and Pat-Tree topology is also presented. These evaluations are done by utilizing NS-2, a tool that has been widely used in the computer network design.
机译：片上系统（SoC）设计提供了集成解决方案，以解决电信，多媒体等方面的挑战性设计问题。当前和将来的SoC是使用预先称为内核的组件设计的。内核之间的通信将成为系统性能的主要瓶颈，因为基于标准的基于硬线总线的通信体系结构在吞吐量，延迟和功耗方面将效率低下。为了解决这个问题，已经提出了一种考虑了线缆的延迟和可靠性问题的分组交换平台，即所谓的片上网络（NoC）。在本文中，我们介绍了互连的网络拓扑，并分析了在带宽限制下特定应用程序的性能。然后，我们比较了将内核映射到Mesh NoC架构的不同方法之间的性能。还介绍了网格和Pat-Tree拓扑之间的比较。这些评估是通过利用NS-2（一种已在计算机网络设计中广泛使用的工具）完成的。

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