A novel wiring design concept called the wire width optimization relating to wire length (WORWIL) method is presented to alleviate wiring delay increase. The problems of increasing interconnection wiring delay due to the wiring resistance in high-performance ECL (emitter coupled logic) circuits and the limitation of the wire utility ratio are solved by this method. Some case studies were performed to confirm the validity of this method. Because of its generality and simplicity, the WORWIL method should be applicable to all types of VLSI design.
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