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Combining mentor graphics' HDL designer FPGA flow with a reconfigurable system on a programmable chip, educational opportunity or insanity?

机译：将指导者图形的HDL设计器FPGA流程与可编程芯片上的可重配置系统结合在一起，带来学习机会还是精神错乱？

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Advances in FPGA technology and in design automation tools have changed the way digital electronics are created. Shematic entry of gates is becoming deprecated by hardware description languages (HDLs) and sophisticated synthesis tools. This requires that the designer have a complete understanding of the entire design flow so that they can utilize the efficiency of HDLs while thinking about the hardware that will be created. This paper reviews three years worth of experience in teaching a two-semester senior/graduate course sequence on Hardware Design Methodologies using the Mentor Graphic's HDL Designer series tools and targeting FPGAs. Currently, all project use an ARM-embedded FPGA as their target. Given the complexity of these new devices, the tools, and only two semesters, we discuss the potential, the limitations/difficulties and the general sanity of this approach.

机译：FPGA技术和设计自动化工具的进步改变了创建数字电子产品的方式。盖茨的Shematic Entry正在弃用硬件描述语言（HDL）和复杂的合成工具。这要求设计人员完全了解整个设计流程，以便它们可以在思考将创建的硬件时使用HDL的效率。本文通过MENTOR Graphic的HDL Designer系列工具和定位FPGA，请评论三年在硬件设计方法上教授两组高级/研究生序列的经验。目前，所有项目都使用ARM-EMBEDDED FPGA作为其目标。鉴于这些新设备的复杂性，工具和只有两个学期，我们讨论了这种方法的潜力，限制/困难和一般理智。

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《》|2003年|p.128-130|共3页
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Hoare; R.R.; Tung; S.C.;
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中图分类无线电电子学、电信技术;
关键词
hardware description languages; field programmable gate arrays; educational courses; teaching; logic CAD; mentor graphics; HDL designer tools; hardware description languages; FPGA technology; programmable chip; design automation tools; digital electronic;

机译：硬件描述语言;现场可编程门阵列;教育课程;教学;逻辑CAD;导师制图; HDL设计器工具;硬件描述语言; FPGA技术;可编程芯片;设计自动化工具;数字电子;

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1. Mentor improves its HDL tool suite for ASIC and FPGA designers [J] . Michael Santarini Electronic Engineering Times . 2002,第1215期

机译：Mentor改进了面向ASIC和FPGA设计人员的HDL工具套件
2. An architecture and design tool flow for embedding a virtual FPGA into a reconfigurable system-on-chip [J] . Wiersema Tobias, Bockhorn Arne, Platzner Marco Computers and Electrical Engineering . 2016,第Null期

机译：用于将虚拟FPGA嵌入可重新配置的片上系统的体系结构和设计工具流程
3. IP: the Key to Turning FPGAs into Programmable System Chips [J] . Timothy W. Colleran Integrated System Design . 1998,第110期

机译：IP：将FPGA变成可编程系统芯片的关键
4. Combining mentor graphics' HDL designer FPGA flow with a reconfigurable system on a programmable chip, educational opportunity or insanity? [C] . Raymond R. Hoare, Shen C. Tung International Conference on Microelectronic Systems Education . 2003

机译：将导师图形的HDL Designer FPGA流与可编程芯片，教育机会或疯狂的可重新配置系统相结合吗？
5. Combined airflow and energy simulation program for building mechanical system design. [D] . Novoselac, Atila. 2005

机译：结合气流和能量模拟程序进行建筑机械系统设计。
6. Combining a Chip-Mate nESI Ion Source with Make-Up Flow Strategy for Increased System Robustness and Sensitivity in nLC-nESI-MS [O] . C. Wang, J. Jones, S.J. Prosser, 2014

机译：结合芯片匹配的nESI离子源和补给流策略以提高nLC-nESI-MS中的系统鲁棒性和灵敏度
7. Tasks Scaling with Chameleon© C2HDL Design Tool in Self-Configurable Computer Systems Based on Partially Reconfigurable FPGAs [O] . Anatoliy Melnyk, Viktor Melnyk, Liubomyr Tsyhylyk 2016

机译：任务用Chameleon进行扩展©C2HDL设计工具，基于部分可重新配置的FPGA

Combining mentor graphics' HDL designer FPGA flow with a reconfigurable system on a programmable chip, educational opportunity or insanity?

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