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Design of a high speed low power linear convolution circuit using McCMOS technique

机译：MCCMOS技术设计高速低功率线性卷积电路

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This paper proposes an efficient design technique of high performance linear convolution of two finite length sequences using Multiple Channel CMOS technique. McCMOS technique uses non-minimum length transistors which offer the possibility of achieving excellent leakage control in nano-scale CMOS design with a very modest increase in area and switched capacitance. This paper approaches the linear convolution technique of two finite length sequences as the conventional multiplication procedure A TG array based novel architecture has been proposed for the implementation of the partial products of the multiplication of two input sequences which gives enormously better performance in terms of the power and speed compared to the conventional design. Thorough simulations of the proposed architecture of linear convolution show that the PDP is reduced approximately 77–97% than the conventional linear convolution design. The proposed technique will be very useful in different applications of time and space domains in digital image and signal processing where power and delay are the main area of concerns.
机译：本文采用了一种使用多通道CMOS技术的两个有限长度序列高性能线性卷积的高效设计技术。 MCCMOS技术采用非最小长度晶体管，该晶体管提供了在纳米级CMOS设计中实现出色的漏电控制，具有非常适度的区域和开关电容的增加。本文接近了两个有限长度序列的线性卷积技术，作为传统的乘法过程，已经提出了基于TG阵列的新颖架构，用于实现两个输入序列乘法的部分产品，这在功率方面提供了极大的性能与传统设计相比的速度。彻底模拟建议的线性卷积架构表明，PDP比传统的线性卷积设计减少约77-97％。该技术在数字图像中的时间和空间域的不同应用中非常有用，信号处理是电力和延迟的主要问题。

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