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Hardware-Accelerated Concurrent Fault Simulation: Eventflow Computing versus Dataflow Computing

机译：硬件加速的并行故障仿真：事件流计算与数据流计算

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摘要

MuSiC, the highly-parallel Munich Simulation Computer, represents an approach for hardware-accelerated logic simulation by applying concepts developed for dataflow architectures to high-speed simulation of digital systems. This approach exploiting parallelism inherent in a design is most efficiently. In comparison to two different dataflow computation schemes and their hardware-accelerated implementations, this paper shows that the strategy of compiler-driven simulation can be combined with the concept of event-(activity)-directed simulation (selective trace simulation) not only for logic simulation but also for concurrent fault simulation. Experiments indicate that there is a performance advantage of eventflow computing over the algorithmi-cally simpler dataflow computing schemes but the advantage is limited, since dataflow computing performance of a MuSiC version with 256 Processing Units already is in the range of 10~7 to 10~8 test-vectors times gates evaluated per second.
机译：高度并行的慕尼黑仿真计算机MuSiC通过将为数据流体系结构开发的概念应用于数字系统的高速仿真，代表了一种硬件加速逻辑仿真的方法。这种利用设计中固有的并行性的方法是最有效的。与两种不同的数据流计算方案及其硬件加速的实现相比，本文表明，编译器驱动的仿真策略可以与事件（活动）定向仿真（选择性跟踪仿真）的概念相结合。仿真，也可用于并发故障仿真。实验表明，与算法简单的数据流计算方案相比，事件流计算具有性能优势，但优势有限，因为具有256个处理单元的MuSiC版本的数据流计算性能已经在10〜7至10〜范围内。每秒评估8个测试向量乘以门。

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