We review the state of the lithographic and process simulation methods employed for full-chip printability analysis and the related techniques of multi-layer design corrections for improved silicon manufacturability. Aerial image simulation methods are presented first. SOCS (Sum Of Coherent Systems) method is analyzed for the various illumination systems. Optical diameter is singled out as a main factor affecting the simulation accuracy and speed. Then new resist processing model, called VTR-E (Extended Variable Threshold Resist, patents pending), is introduced. The model accuracy is studied by comparison of predicted and measured EPEs (Edge Placement Errors) on a layout pattern. Significant advantages of VTR-E are demonstrated for the line-end EPE calculations. The etch-induced CD variation is captured by VEB (Variable Etch Bias) model. It is based on the assumption that the etch bias depends on the two layout parameters, the resist density and the effective trench width. The model explains short-range etch CD bias in a wide diapason of pattern parameters. In the end, the important applications of a large area process simulator are presented, including via overlap analysis, side-lobe/dimple detection, and PSM attenuation for vias/contacts.
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