In this paper, the geometrical effects of crossing under-layer interconnects on the upper-layer signal integrity are investigated, using several deep-submicron interconnect test structures. Signal integrity of global lines are affected not only by the under-layer geometry itself, but also by the unwilling changes such as pattern-dependent IMD thickness and the metal shape of crossing under-layer lines. Our study suggests that these geometrical effects can cause substantial (more than 10%) under-estimation or over-estimation in the delay and the crosstalk of upper-layer interconnects depending on the under-layer patterns. We also find that the relation between signal integrity and process changes can be expressed as a function of the under-layer wire density on a fabrication. These pattern- and process-dependent correlation of interconnect parasitics should become another considering issue for accurate estimation of chip performance, so that a proper tool calibration should be needed.
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