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首页> 外文会议>International VLSI multilevel interconnection conference;VMIC >Low temperature CVDTiN deposition combined with N_2/H_2 plasma treatment to prevent Al extrusion
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Low temperature CVDTiN deposition combined with N_2/H_2 plasma treatment to prevent Al extrusion

机译：低温CVDTiN沉积结合N_2 / H_2等离子体处理可防止Al挤出

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摘要

Low temperature CVDTiN deposition combined with a suitable N_2/H_2 ratio plasma treatment has been demonstrated to prevent Al extrusion in the advanced VLSI metallization technology. By means of decreasing the deposited temperature from 450°C to 410?, not only the risk of Al extrusion from the underneath metal line could be reduced dramatically, but the step coverage of the contact vias was improved greatly because of the lower deposition rate. However, this lower temperature process leads to a higher resistivity CVDTiN film than that of the higher temperature process even with the same thickness. We therefore apply a multi-layer plasma treatment with different N_2/H_2 gas flow ratios to overcome this disadvantage. With the suitable plasma-treatment, the Rs of CVDTiN films will decrease effectively. Experimental results also show that films with good plasma treatment usually lead to a uniform tungsten grain size formed in the nucleation step of W plug without affecting the contact resistance. The uniform grain size of tungsten may reduce the worm-hole failures of W plug.
机译：在先进的VLSI金属化技术中，低温CVDTiN沉积与合适的N_2 / H_2比等离子体处理相结合可防止Al挤出。通过将沉积温度从450°C降至410°C，不仅可以显着降低铝从金属下层挤出的风险，而且由于降低了沉积速率，大大提高了接触通孔的台阶覆盖率。然而，即使具有相同的厚度，该较低温度的过程也导致比较高温度的过程更高的电阻率的CVDTiN膜。因此，我们采用具有不同N_2 / H_2气体流量比的多层等离子体处理来克服此缺点。通过适当的等离子体处理，CVDTiN膜的Rs将有效降低。实验结果还表明，经过良好等离子处理的薄膜通常会导致在W塞形核步骤中形成均匀的钨晶粒尺寸，而不会影响接触电阻。钨的均匀晶粒尺寸可以减少W塞的虫孔故障。

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