The Influence of Inter-Metal Dielectric and HDP Passivation Layer on Device Performance

机译：金属间介电层和HDP钝化层对器件性能的影响

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The properties of IMD layer show great impact on trap-up rate in FLASH device. In the current study, SA CVD oxide formed with a relatively high ratio of O3/TEOS ratio show high oxide densities and low etching rate; the oxide structure consist of low water content, leading to low electron trap rate. Furthermore, HDP oxide deposited with a relatively high bias power induces dense film structure in passivation layer, leading to further reduction in electron trap rate.

机译：IMD层的特性对FLASH器件的俘获率有很大的影响。在目前的研究中，以较高的O3 / TEOS比形成的SA CVD氧化物具有高的氧化物密度和低的刻蚀速率。氧化物结构由低水含量组成，导致电子陷阱率低。此外，以相对较高的偏置功率沉积的HDP氧化物在钝化层中引起致密的膜结构，从而导致电子俘获速率的进一步降低。

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《International VLSI multilevel interconnection conference;VMIC》|2000年|p.407-410|共4页
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Chyi-Tsong Ni; David Yang; Eric Su; Kevin Tsai;
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中图分类无线电电子学、电信技术;
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The Influence of Inter-Metal Dielectric and HDP Passivation Layer on Device Performance

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