Differences in pattern density at the die level and sub-die level can cause large differences in local polish rate. Due to the tighter process control requirements anticipated as the process window narrows, the use of a test site located in the scribe line is not always a viable option. There is a strong need to expand the available choice of measurement sites to enable thickness monitoring at locations dictated by process control requirements- Therefore, thickness measurements should take place at the locations of interest within the die, using the sites available there. Such sites are often patterned, consisting of multiple adjacent layer stacks. This paper presents a novel measurement technique for measuring the thickness of dielectric layers or other layers commonly used in back-end-of-line processes, which dramatically increases the available choice of measurement locations, enabling thickness measurements on various regularly patterned backgrounds previously attainable only by destructive cross-sectional measurements.
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