Parallel - pipelined radix-2² FFT architecture for real valued signals

机译：并行-实数信号的流水线基数2 ^{2 FFT架构}

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This paper presents a novel parallel-pipelined architecture for the computation of real valued fast Fourier transform (RFFT). The proposed architecture takes advantage of the redundancy of some computations with respect to complex FFT along with low multiplicative complexity of the radix-2² architecture. Folding transformation is used to derive a novel parallel-pipelined architecture by exploiting the redundancy in the modified flow graph. The proposed parallel architecture requires log4N − 1 complex multipliers and N − 1 complex delay elements.

机译：本文提出了一种新颖的并行流水线架构，用于计算实值快速傅里叶变换（RFFT）。所提出的体系结构利用了关于复杂FFT的一些计算的冗余以及radix-2 ^{2 体系结构的低乘法复杂性。通过利用修改后的流程图中的冗余，可将折叠变换用于推导新颖的并行流水线架构。提出的并行架构需要log 4 N-1个复数乘法器和N-1个复数延迟元素。}

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《Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers》|2010年|p.1274-1278|共5页
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Ayinala Manohar; Parhi Keshab K.;
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正文语种
中图分类通信理论;
关键词
FFT; Folding; Parallel Processing; Pipelining; Real Signals; radix-2sup2/sup;

机译：FFT;折叠;并行处理;流水线;实信号;基数2 ^{2 ;}

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专利

1. A Novel Memory-Based FFT Architecture for Real-Valued Signals Based on a Radix-2 Decimation-In-Frequency Algorithm [J] . Ma Zhen-Guo, Yin Xiao-Bo, Yu Feng Circuits and Systems II: Express Briefs, IEEE Transactions on . 2015,第9期

机译：基于Radix-2频率抽取算法的新颖的基于存储器的实值信号FFT架构
2. A Pipelined FFT Architecture for Real-Valued Signals [J] . Garrido M.Parhi K.K.Grajal J. Circuits and Systems I: Regular Papers, IEEE Transactions on . 2009,第12期

机译：用于实值信号的流水线FFT架构
3. Radix-2 FFT-pipeline architecture with reduced noise-to-signal ratio [J] . Storn R. IEE Proceedings. Part K . 1994,第2期

机译：具有降低的信噪比的Radix-2 FFT管线架构
4. Parallel pipelined FFT architecture for real valued signals using radix-2 [C] . Shivaraja Kumar Mali, Manjunath C Lakkannavar IEEE International Conference on Recent Trends In Electronics Information Communication Technology . 2016

机译：使用基数2的并行流水线FFT架构，用于实值信号
5. DWT and DCT parallel-pipelined architectures for real time applications. [D] . Alam, Mehboob. 2003

机译：DWT和DCT并行流水线架构，用于实时应用。
6. Parallel 2D FFT implementation on FPGA suitable for real-time MR image processing [O] . Limin Li, Alice M. Wyrwicz -1

机译：适用于实时MR图像处理的FPGA并行2D FFT实现
7. A Pipelined FFT Architecture for Real-Valued Signals [O] . Garrido, Mario, Parhi, Keshab. K., Grajal, Jesus 2009

机译：用于实值信号的流水线FFT架构

Parallel - pipelined radix-22 FFT architecture for real valued signals

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Parallel - pipelined radix-2² FFT architecture for real valued signals