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首页> 外文会议>2011 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip >A self-reconfigurable platform for general purpose image processing systems on low-cost spartan-6 FPGAs
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A self-reconfigurable platform for general purpose image processing systems on low-cost spartan-6 FPGAs

机译：用于低成本spartan-6 FPGA的通用图像处理系统的可自我重新配置平台

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There is still no partial reconfiguration tool support on low-cost Field Programmable Gate Arrays (FPGAs) such as old-fashioned Spartan-3 and state-of-the-art Spartan-6 FPGA families by Xilinx. This forces the designers and engineers, who are using the partial reconfiguration capability of FPGAs, to use expensive families such as Virtex-4, Virtex-5 and Virtex-6 which are officially supported by partial reconfiguration (PR) software. Moreover, Xilinx still does not offer a portable, dedicated self-reconfiguration engine for all of the FPGAs. Self-reconfiguration is achieved with general-purpose processors such as MicroBlaze and PowerPC which are too overqualified for this purpose. In this study, we propose a new self-reconfiguration mechanism for Spartan-6 FPGAs. This mechanism can be used to implement large and complex designs on small FPGAs as chip area can be dramatically reduced by exploiting the dynamic partial reconfiguration feature for on-demand functionality loading and maximal utilization of the hardware. This approach is highly attractive for designing low-cost compute-intensive applications such as high performance image processing systems. For Spartan-6 FPGAs, we have developed hard-macros and exploited the self-reconfiguration engine, compressed Parallel Configuration Access Port (cPCAP) [1], that we designed for Spartan-3. The modified cPCAP core with block RAM controller, bitstream decompressor unit and Internal Configuration Access Port (ICAP) Finite State Machine (FSM) occupies only about 82 of 6,822 slices (1.2% of whole device) on a Spartan-XC6SLX45 FPGA and it achieves the maximum theoretical reconfiguration speed of 200MB/s (ICAP, 16-bit at 100MHz) proposed by Xilinx. We have also implemented a Reconfigurable Processing Element (RPE) whose arithmetic unit can be reconfigured on-the-fly. Multiple RPEs can be utilized to design a General Purpose Image Processing System (GPIPS) that can implement a number of different algorithms during runtime. As --an illustrative example, we programmed the GPIPS on Spartan-6 for switching between two applications on-demand such as two-dimensional filtering and block-matching.
机译：低成本的现场可编程门阵列（FPGA），例如Xilinx的老式Spartan-3和最先进的Spartan-6 FPGA系列，仍不支持部分重新配置工具。这迫使正在使用FPGA的部分重新配置功能的设计人员和工程师使用昂贵的系列，例如由部分重新配置（PR）软件正式支持的Virtex-4，Virtex-5和Virtex-6。此外，Xilinx仍未为所有FPGA提供可移植的专用自重配置引擎。使用MicroBlaze和PowerPC之类的通用处理器可实现自我重新配置，而这些通用处理器对于此目的而言过于合格。在这项研究中，我们为Spartan-6 FPGA提出了一种新的自重配置机制。这种机制可用于在小型FPGA上实现大型和复杂的设计，因为通过利用动态部分重新配置功能来按需加载功能和最大程度地利用硬件，可以显着减少芯片面积。对于设计低成本计算密集型应用程序（例如高性能图像处理系统）而言，这种方法极具吸引力。对于Spartan-6 FPGA，我们开发了硬宏，并利用了为Spartan-3设计的自重配置引擎，压缩的并行配置访问端口（cPCAP）[1]。带有块RAM控制器，比特流解压缩器单元和内部配置访问端口（ICAP）有限状态机（FSM）的经过修改的cPCAP内核在Spartan-XC6SLX45 FPGA上仅占6,822个切片中的约82个（占整个设备的1.2％），并且实现了Xilinx提出的最大理论重新配置速度为200MB / s（ICAP，100MHz时为16位）。我们还实现了可重配置处理单元（RPE），其算术单元可以即时进行重配置。可以使用多个RPE设计通用图像处理系统（GPIPS），该系统可以在运行时实现多种不同的算法。作为 - -- 作为一个说明性示例，我们在Spartan-6上对GPIPS进行了编程，以按需在两个应用程序之间进行切换，例如二维过滤和块匹配。

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