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A 7Gb/s/pin GDDR5 SDRAM with 2.5ns Bank-to-Bank Active Time and No Bank-Group Restriction

机译：7GB / S /引脚GDDR5 SDRAM，2.5NS银行到银行的积极时间，没有银行集团限制

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摘要

In the development of 3D graphic systems for higher resolution and more realistic modeling and rendering, graphic memories also have been playing a critical role to offer the required high bandwidth. Currently, GDDR5 SDRAM's provide with 7Gbps per pin speed [1], reaching their physical limit originated from single-ended signaling nature: noise in reference voltage and power, and channel crosstalk. Especially, the channel crosstalk takes a dominating portion in 7Gbps timing budget, becoming the main barrier for further speed improvement. Although there has been research on crosstalk canceller in memory interface [2], it imposed stringent restrictions on signal ordering and trace length in PCB and package routing, and had limited performance. Therefore, improving the efficiency of DRAM core draws more attention than pin bandwidth now.
机译：在高度分辨率和更现实的建模和渲染的3D图形系统的开发中，图形存储器也一直在发挥关键作用，以提供所需的高带宽。目前，GDDR5 SDRAM提供了每个引脚速度7Gbps [1]，达到其物理极限，起源于单端信令性质：参考电压和电源的噪声，以及通道串扰。特别是，通道串扰采用7Gbps定时预算中的主导部分，成为进一步速度改善的主要障碍。虽然在存储器接口[2]中一直研究串扰消除器[2]，但它对PCB和包路由中的信号排序和跟踪长度进行了严格的限制，性能有限。因此，提高DRAM核心的效率比现在比PIN带宽更多的关注。

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