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Design of PCI-104 bus interface of lowpower embedded CPU based on FPGA

机译：基于FPGA的低功耗嵌入式CPU PCI-104总线接口设计

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摘要

In the application of some embedded systems such as the ship-borne routers, ATM machines and so on, many low-power embedded CPU needs connection with PCI-104 bus. However, these low-power embedded CPUs don't have the bus interface of PCI-104 (PCI). In order to solve this problem, this paper designs FPGA-based PCI-104 bus interfaces of the low-power embedded CPU. Through the analysis of PCI-104 bus protocol and the corresponding interface signal sequence, the method of Top_Down is applied to the modeling of the seven functional modules of PCI-104 bus interface such as the configuration register module, base address check module, state machine module, etc. Besides, in consideration that these CPUs can also be taken as the coprocessors, the master and target device interfaces of PCI-104 bus are programmed with the utilization of Verilog language, and the finite-state machine of the master device and the target device is structured in detail. Through the Modelsim simulation verification, it has been proved that the interface can meet the timing requirements of the PCI-104 bus specification, so as to connect these low-power embedded CPUs with PCI-104 bus expansion board. It also can realize to upgrade CPU on the PCI-104 bus board.
机译：在某些嵌入式系统的应用中，例如船载路由器，ATM机等，许多低功耗嵌入式CPU需要与PCI-104总线连接。但是，这些低功耗嵌入式CPU没有PCI-104（PCI）的总线接口。为了解决这个问题，本文设计了基于FPGA的低功耗嵌入式CPU的PCI-104总线接口。通过对PCI-104总线协议和相应接口信号序列的分析，将Top_Down方法应用于PCI-104总线接口的七个功能模块的建模，例如配置寄存器模块，基地址检查模块，状态机。此外，考虑到这些CPU也可以用作协处理器，因此使用Verilog语言对PCI-104总线的主设备接口和目标设备接口进行编程，并使用主设备的有限状态机进行编程。目标设备的详细结构。通过Modelsim仿真验证，证明该接口可以满足PCI-104总线规范的时序要求，从而可以将这些低功耗嵌入式CPU与PCI-104总线扩展板连接。它还可以实现升级PCI-104总线板上的CPU。

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