Silicon nanowire devices with widths below 5 nm

机译：硅纳米线装置，宽度低于5 nm

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This paper describes a robust process for the fabrication of highly doped Silicon-On-Insulator nanowires and devices. The process uses electron-beam lithography, lowdamage dry etch and controlled thermal oxidation to deliver consistent, reproducible and reliably nanowires of nominal widths from 100 nm down to sub-5 nm etched to a depth of 55 nm in silicon. Initial electrical measurements indicate metallic behavior for the widest wires and below a particular width, the wires become depleted showing electrical behaviour consistent with Coulomb blockade at room temperature.

机译：本文介绍了制造高掺杂的绝缘体纳米线和装置的稳健方法。该方法采用电子束光刻，低峰值干蚀刻和受控的热氧化，以从100nm到沉积到55nm的深度为55nm的副5nm的标称宽度的一致性，可再现和可靠的纳米线。初始电测量表示最宽导线和低于特定宽度的金属行为，导线耗尽，显示与室温下与库仑封锁一致的电动行为。

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《IEEE International Conference on Nanotechnology》|2012年||共4页
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Mirza M. M.; Velha P.; Ternent G.; Zhou H. P.; Docherty K. E.; Paul D. J.;
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中图分类 TB383-53;
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入库时间 2022-08-20 22:08:44

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2. Silicon Nanowire Transistors with a Channel Width of 4 nm Fabricated by Atomic Force Microscope Nanolithography [J] . Martinez J, Martinez RV, Garcia R Nano letters . 2008,第11期

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3. Effects of Asymmetric Local Joule Heating on Silicon Nanowire-Based Devices Formed by Dielectrophoresis Alignment Across Pt Electrodes [J] . Hsiang-Hsi Ho, Chun-Lung Lin, Wei-Che Tsai, Nanoscale Research Letters . 2018,第1期

机译：不对称局部焦耳加热对跨Pt电极介电电泳排列形成的硅纳米线基器件的影响
4. Silicon nanowire devices with widths below 5 nm [C] . Mirza M. M., Velha P., Ternent G., 2012 12th IEEE International Conference on Nanotechnology. . 2012

机译：宽度小于5 nm的硅纳米线器件
5. Nanowire-based devices for electronic and optical applications: Solution-gated silicon nanowire field effect transistors and one-dimensional gold nanoparticle arrays [D] . Hu, Wenchong 2010

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6. Effects of Asymmetric Local Joule Heating on Silicon Nanowire-Based Devices Formed by Dielectrophoresis Alignment Across Pt Electrodes [O] . Hsiang-Hsi Ho, Chun-Lung Lin, Wei-Che Tsai, 2018

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7. Fully CMOS-compatible top-down fabrication of sub-50 nm silicon nanowire sensing devices [O] . Georgiev Yordan M., Petkov Nikolay, McCarthy Brendan, 2014

机译：完全兼容CMOS的自上而下的低于50 nm硅纳米线感测设备的制造

Silicon nanowire devices with widths below 5 nm

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