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首页> 外文会议>European Conference on Radiation and Its Effects on Components and Systems >Investigation into SEU Effects and Hardening Strategies in SRAM Based FPGA
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Investigation into SEU Effects and Hardening Strategies in SRAM Based FPGA

机译：SRAM基于FPGA的SEU效应和硬化策略的调查

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The mitigation of single event upset (SEU) in SRAM based Field Programmable Gate Array (FPGA) is increasingly important as it is widely used in radiation environments such as space. As D flip-flop (DFF) and memory (including Block RAM and Configuration RAM) are the key elements in FPGAs, it is crucial to develop radiation hardening techniques for enhanced reliability of the DFF and memory. A novel hardened memory design for FPGA is proposed with multi-bit upset (MBU) protection. We further developed two prototype FPGA chips, one with and the other without SEU hardening for comparison. The FPGA chips are fabricated in a standard 0.13μm CMOS process and have a volume of 3 million equivalent logic gates. In contrast to the base FPGA, the SEU cross section of the memory in the hardened FPGA is at least three orders of magnitude lower. Also, no SEU upsets are observed in the DFF of the hardened FPGA.
机译：SRAM基场可编程门阵列（FPGA）中的单一事件镦粗（SEU）的减轻越来越重要，因为它广泛用于诸如空间的辐射环境中。作为D触发器（DFF）和存储器（包括块RAM和配置RAM）是FPGA中的关键元件，对于开发辐射硬化技术来说是为了提高DFF和存储器的可靠性至关重要。提出了一种用于FPGA的新型硬化内存设计，具有多级镦粗（MBU）保护。我们进一步开发了两个原型FPGA芯片，一个与另一种原型FPGA芯片，没有SEU硬化进行比较。 FPGA芯片以标准的0.13μmCMOS工艺制造，具有300万等同逻辑门。与基础FPGA相反，硬化FPGA中存储器的SEU横截面是至少三个数量级。此外，在硬化FPGA的DFF中没有观察到SEU UPSET。

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