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Run-Time FPGA Health Monitoring using Power Emulation Techniques

机译：利用电力仿真技术运行时FPGA健康监控

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In recent years research on long-term reliability of FPGAs intensified significantly. This results from the broad usage of these devices for applications that come with high long-term stability constraints while being physically inaccessible. Several error checking and detection methods have been published to cope with degradation over time but these either force the FPGA to halt for exhaustive tests or their coverage decreases significantly. This paper presents an early view on a multi-disciplinary approach for run-time reliability monitoring and self-repairing using state-of-the-art power-emulation and FPGA partial reconfiguration techniques. Furthermore we propose a novel device aging detection mechanism using these power emulation techniques. It is meant to provide an outlook on the current state-of-the-art and future possibilities using these techniques for a combined reliability effort.
机译：近年来，FPGA的长期可靠性研究显着强化。这导致这些设备的广泛用途对于具有高长期稳定性约束的应用，同时物理无法访问。已经公布了几种错误检查和检测方法以应对降低随时间的降级，但是这些迫使FPGA停止用于详尽的测试或其覆盖率显着降低。本文提出了一种关于使用最先进的电源仿真和FPGA部分重新配置技术的运行时可靠性监测和自修复方法的多学科方法的早期视图。此外，我们提出了一种使用这些功率仿真技术的新型设备老化检测机构。它旨在提供目前最先进的和未来可能性的展望，使用这些技术进行组合可靠性努力。

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