3D implemented SRAM/DRAM hybrid cache architecture for high-performance and low power consumption

机译：3D实现了SRAM / DRAM混合缓存架构，用于高性能和低功耗

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This paper introduces our research status focusing on 3D-implemented microprocessors. 3D-IC is one of the most interesting techniques to achieve high-performance, low-power VLSI systems. Stacking multiple dies makes it possible to implement microprocessor cores and large caches (or DRAM) into the same chip. Although this kind of integration has a great potential to bring a breakthrough in computer systems, its efficiency strongly depends on the characteristics of target application programs. Unfortunately, applying die stacking implementation causes performance degradation for some programs. To tackle this issue, we introduce a novel cache architecture consisting of a small but fast SRAM and a stacked large DRAM. The cache attempts to adapt to varying behavior of application programs in order to compensate for the negative impact of the die stacking approach.

机译：本文介绍了我们的研究状态，专注于3D实现的微处理器。 3D-IC是实现高性能低功耗VLSI系统最有趣的技术之一。堆叠多个模具使得可以将微处理器核和大型缓存（或DRAM）实施到同一芯片中。虽然这种整合具有巨大的潜力，可以在计算机系统中带来突破，但其效率强烈取决于目标应用程序的特征。不幸的是，应用模具堆叠实现会导致某些程序的性能下降。为了解决这个问题，我们介绍了一个小型缓存架构，包括一个小但快速的SRAM和堆积的大型DRAM。缓存尝试适应应用程序的不同行为，以便补偿模具堆叠方法的负面影响。

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《IEEE International Midwest Symposium on Circuits and Systems》|2011年||共4页
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Inoue Koji; Hashiguchi Shinya; Ueno Shinya; Fukumoto Naoto; Murakami Kazuaki;
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1. High-performance/Low-power Cache Architectures for Merged DRAM/Logic LSIs [J] . Koji Inoue, Tohru Ishihara, Koji Kai 情報処理学会論文誌 . 2001,第3期

机译：合并的DRAM /逻辑LSI的高性能/低功耗高速缓存架构
2. Controller Architecture for Low-Power, Low-Latency DRAM With Built-in Cache [J] . Zhi-Yong Liu, Hsiu-Chuan Shih, Bing-Yang Lin, Design & Test of Computers, IEEE . 2017,第2期

机译：具有内置缓存的低功耗，低延迟DRAM的控制器架构
3. Using CMOS Sub-Micron Technology VLSI Implementation of Low Power, High Speed SRAM Cell and DRAM Cell [J] . Viplav A. Soliv, Ajay A. Gurjar International Journal of VLSI Design & Communication Systems . 2011,第4期

机译：使用CMOS亚微米技术的VLSI实现低功耗，高速SRAM单元和DRAM单元
4. 3D implemented SRAM/DRAM hybrid cache architecture for high-performance and low power consumption [C] . Inoue Koji, Hashiguchi Shinya, Ueno Shinya, The 54th IEEE International Midwest Symposium on Circuits and Systems . 2011

机译：3D实现的SRAM / DRAM混合缓存架构，可实现高性能和低功耗
5. Low power and process variation aware SRAM and Cache design fault tolerance in SRAM circuit, architecture and organization. [D] . Sasan, Avesta. 2010

机译：低功耗和工艺变化感知型SRAM和Cache在SRAM电路，架构和组织中的设计容错能力。
6. In-DRAM Cache Management for Low Latency and Low Power 3D-Stacked DRAMs [O] . Ho Hyun Shin, Eui-Young Chung 2019

机译：用于低延迟和低功耗3D堆叠DRAM的DRAM中缓存管理
7. Using CMOS Sub-Micron Technology VLSI Implementation of Low Power, High Speed SRAM Cell and DRAM Cell [O] . Mr.Viplav A. Soliv, Dr. Ajay A. Gurjar2 2011

机译：采用CmOs亚微米技术VLsI实现低功耗，高速sRam单元和DRam单元

3D implemented SRAM/DRAM hybrid cache architecture for high-performance and low power consumption

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