Cryptographic systems are vulnerable to Differential Power Analysis (DPA) attacks. Making the time instant of executing certain operation unpredictable is an efficient way to counteract DPA attacks. The variation of the execution time instant is called temporal jitter. In principle, the more the temporal jitter appears, the less probability the attack succeeds. In this paper, we propose specific pipeline structures which have variable latency and variable number of cascaded registers inserted in between two adjacent functional blocks. Temporal-jitter can be exploited to counteract DPA attacks in such pipelines. We will analyze their effectiveness to resist attacks. The proposed approaches can be realized in both ASIC and FPGA implementations because their structures can be easily and quickly changed without using reconfiguration facility. To show the applicability, the AES encryption algorithm was implemented and the function was successfully verified.
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