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首页> 外文会议>IEEE International Midwest Symposium on Circuits and Systems >Integration of cache data allocation and voltage/frequency scaling for temperature-constrained multi-core systems with 3-D stacked cache memory
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Integration of cache data allocation and voltage/frequency scaling for temperature-constrained multi-core systems with 3-D stacked cache memory

机译：高速缓存数据分配和电压/频率缩放的集成温度约束多核系统，具有3-D堆叠缓存存储器

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Three-dimensional (3-D) memory stacking can resolve memory bandwidth challenges in chip multi-cores by stacking multiple dies of cache memory via inter-die wires between the stacked memories and multiprocessors. However, high power density (i.e., power dissipation per unit volume) due to the high integration incurs temperature-related problems in reliability, power consumption, performance, and system cooling cost. In this paper, we propose a solution to maximize the instruction throughput for temperature-constrained multi-core systems with 3-D stacked cache memory. The proposed method combines cache data allocation (including power gating of cache memory banks) and voltage/frequency scaling of cores in a temperature-aware manner. Experimental results show that the proposed method offers performance improvement in terms of instructions per second (IPS) compared with existing methods that only perform either cache data allocation or voltage/frequency scaling.
机译：三维（3-D）存储器堆叠可以通过在堆叠的存储器和多处理器之间通过阵线堆叠多次高速缓冲存储器来解决芯片多核中的存储带宽挑战。然而，由于高集成度导致可靠性，功耗，性能和系统冷却成本高，电力密度高功率密度（即每单位音量的功耗）。在本文中，我们提出了一种解决方案来最大限度地提高具有3-D堆叠高速缓冲存储器的温度受限多核系统的指令吞吐量。该方法将高速缓存数据分配（包括高速缓存存储体的功率门控）和核心的电压/频率缩放以温度感知的方式组合。实验结果表明，与仅执行高速缓存数据分配或电压/频率缩放的现有方法相比，该方法在每秒指令（IPS）方面提供性能改进。

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