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首页> 外文会议>International Symposium on Telecommunications >High-frequency Direct Digital Frequency Synthesizer design with non-uniform sine-weighted Digital-to-Analog Convertor
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High-frequency Direct Digital Frequency Synthesizer design with non-uniform sine-weighted Digital-to-Analog Convertor

机译：具有非均匀正弦加权数模转换器的高频直接数字频率合成器设计

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摘要

In this paper, a novel Direct Digital Frequency Synthesizer (DDFS) based on using non-uniform segmentation in sine-weighted Digital-to-Analog Convertor (DAC) is proposed. To generating beyond Nyquist frequency signal, parallel DACs with Return-To-Zero (RTZ) technique are used. In conventional DDFSs for generating signal, a Phase to Sine Mapper (PSM) is used that often includes a look-up table memory. Because of the speed and area bottleneck of the look-up table memory, sine-weighted-DAC is used. Generating sampled-data signals near the Nyquist rate frequency requires a sharp smoothing filter. For avoiding requiring a sharp filter and generating signals beyond the Nyquist rate, parallel DACs and RTZ technique are used that causes speed relaxation in single DACs. To reduce area and power, non-uniform segmentation by modified sine weighted DAC is proposed. This technique causes to reduce DACs area by %30.13, and nearly the same amount of reduction in consumed dynamic power. In the simulation in 0.18μm CMOS technology with an external clock output frequency of 2GHz, the DDFS with 8-bit frequency resolution can generate output sine signal of 984.375 MHz frequency, to see the worst case, giving a Spurious Free Dynamic Range (SFDR) of 52.1dB.
机译：本文提出了一种基于正弦加权数模转换器（DAC）中非均匀分段的新型直接数字频率合成器（DDFS）。为了产生超过奈奎斯特频率的信号，使用了具有归零（RTZ）技术的并行DAC。在用于产生信号的常规DDFS中，使用了一个正弦映射器（PSM），该相位器通常包括一个查找表存储器。由于查找表存储器的速度和面积瓶颈，因此使用了正弦加权DAC。产生接近奈奎斯特速率频率的采样数据信号需要一个尖锐的平滑滤波器。为了避免使用尖锐的滤波器并生成超出奈奎斯特速率的信号，使用了并行DAC和RTZ技术，这会导致单个DAC出现速度松弛。为了减小面积和功耗，提出了通过改进的正弦加权DAC进行非均匀分割的方法。该技术可将DAC面积减小30.13％，并减少几乎相同的动态功耗消耗。在外部时钟输出频率为2GHz的0.18μmCMOS技术的仿真中，具有8位频率分辨率的DDFS可以产生984.375 MHz频率的输出正弦信号，以观察最坏的情况，从而给出无杂散动态范围（SFDR） 52.1dB。

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