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A Progressive Dual-Rail Routing Repair Approach for FPGA Implementation of Crypto Algorithm

机译：FPGA加密算法实现的渐进式双轨路由修复方法

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摘要

Side Channel Analysis (SCA), which has gained wide attentions during the past decade, has arisen as one of the most critical metrics for the cryptographic algorithm security evaluation. Typical SCA analyzes the data-dependent variations inspected from side channel leakages, such as power and electromagnetism (EM), to disclose intra secrets from cryptographic implementations on varying platforms, like microprocessor, FPGA, etc. Dual-rail Precharge Logic (DPL) has proven to be an effective logic-level countermeasure against classic correlation analysis by means of dual-rail compensation protocol. However, the DPL design is hard to be automated on FPGA, and the only published approach is subject to a simplified and partial AES core. In this paper, we present a novel implementation approach applied to a complete AES-128 crypto algorithm. This proposal bases on a partition mechanism which splits the whole algorithm to submodules and transform individuals to DPL format respectively. The main flavor lies within its highly symmetric dual-rail routing networks inside each block, which significantly reduces the routing bias between each routing pair in DPL. This paper describes the overall repair strategy and technical details. The experimental result shows a greatly elevated success rate during the routing repair phase, from lower than 60% to over 84% for Xilinx Virtex-5 FPGA in SASEBO-GII evaluation board.
机译：在过去的十年中，侧通道分析（SCA）已成为加密算法安全性评估的最关键指标之一。典型的SCA分析从旁通道泄漏（例如功率和电磁（EM））检查的数据相关变化，以揭示在不同平台（例如微处理器，FPGA等）上的加密实现的内部秘密。双轨预充电逻辑（DPL）具有通过双轨补偿协议，它被证明是针对经典相关分析的有效逻辑级对策。但是，DPL设计很难在FPGA上实现自动化，并且唯一公开的方法是使用简化的部分AES内核。在本文中，我们提出了一种适用于完整AES-128加密算法的新颖实现方法。该建议基于一种分区机制，该机制将整个算法拆分为子模块，并将个人分别转换为DPL格式。其主要特色在于每个块内部的高度对称双轨路由网络，这大大降低了DPL中每个路由对之间的路由偏差。本文介绍了整体维修策略和技术细节。实验结果表明，在路由修复阶段，SASEBO-GII评估板中的Xilinx Virtex-5 FPGA的成功率从不到60％提高到超过84％。

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